Ternary Number System Research Articles

ExTern: Boosting RISC-V core performance using ternary encoding

This paper presents an effective μ-architectural design method, called ExTern, to enhance the performance of a RISC-V processor experiencing computation bottlenecks. ExTern involves integrating Canonical Signed Digit (CSD) representation, a ternary number system enabling carry/borrow-free addition/subtraction in constant time O(1), into the RISC-V processor, particularly into the execution stage. Furthermore, it adopts an extended six-stage pipeline architecture to maximize employed encoding benefits, leading to more improvement in overall execution time and throughput. Despite the presence of optimized circuits, such as fast carry chain (CARRY4) modules for binary encoding on FPGA, the customized processor applying ExTern, RISC-VT, showcases remarkable improvement in computation performance. Experimental results demonstrate a 34.3% (12.2%) improvement in working frequency leading to a lower 31% (11.5%) execution time and a 32% (12%) increase in throughput compared to a State-of-the-Art open-source five(six)-stage RISC-V processor.

Digits of powers of 2 in ternary numeral system

We study the digits of the powers of 2 in the ternary number system. We propose an algorithm for doubling numbers in ternary numeral system. Using this algorithm, we explain the appearance of “stairs” formed by 0s and 2s when the numbers $2^n (n=0,1,2, \ldots)$ are written vertically so that for example the last digits are forming one column, the second last digits are forming another column, and so forth. We use the patterns formed by the leftmost digits, and the patterns formed by the rightmost digits to prove that the sizes of these blocks of 0s and 2s are unbounded. We also study how this regularity changes when the digits are taken between the left end and the right end of the numbers.

CNTFET-Based Ternary Multiply-and-Accumulate Unit

Multiply-Accumulate (MAC) is one of the most commonly used operations in modern computing systems due to its use in matrix multiplication, signal processing, and in new applications such as machine learning and deep neural networks. Ternary number system offers higher information processing within the same number of digits when compared to binary systems. In this paper, a MAC is proposed using a CNTFET-based ternary logic number. Specifically, we build a 5-trit multiplier and 10-trit adder as building blocks of two ternary MAC unit designs. The first is a basic MAC which has two methods to implement, serial and pipeline. The second is an improved MAC design that optimizes the number of transistors, offers higher performance and lower power consumption. The designed MAC unit can operate up to 300 MHz. Finally, a comparative study in terms of power, delay, and area variations is conducted under different supply voltages and temperature levels.

Application three-valued logic in symmetric block encryption algorithms

The issues of limiting the use of binary logic for the further development of science engineering are discussed. The effectiveness of the use of the ternary number system at this stage in the development of information technologies is substantiated and shown. A method is proposed for increasing the informational entropy of plaintext by adding random data using ternary logic in the process of symmetric encryption. To reliably hide the added random data, the first transforming function is proposed to choose gamming with a key.

CNTFET design of a multiple-port ternary register file

Ternary number system offers higher information processing within the same number of digits when compared to binary systems. Such advantage motivated the development of ternary processing units especially with CNTFET which offers better power and delay results compared to CMOS-based realization. In this paper, we propose a variety of circuit realizations for the ternary memory elements that are needed in any processor including ternary D-latch, and ternary D-flip-flop. These basic building blocks are then used to design a ternary register file with multiple read and write ports. This paper is an attempt to investigate the performance aspects of using ternary RF to open the gate of more contributions and research in the direction of full ternary computer architecture. The proposed designs have been compared in terms of power, area, and latency at different supply voltages and operating temperatures.

Comparative performance analysis of FPGA-based MAC unit using non-conventional number system in TVL domain for signal processing algorithm

Today, the complication of binary digital hardware system is progressively growing. Due to this fact, new methodologies for efficiently describing and realising the digital systems are explored in this paper. Multi-valued logic methodology offers a few preferences over existing binary digital system. One of the well-known multi-valued logic systems is ternary value logic (TVL) system. It is seen that all kind of digital signal processing (DSP) algorithms widely use multiply-accumulate (MAC) operation for superior digital processing system. To implement high performance DSP algorithms MAC unit is used extensively. In current scenario, it is seen that non-conventional, non-binary number system-based architecture is also exhibited better performance. The example of such non-conventional, non-binary number systems is ternary residue number systems (TRNSs) and double base ternary number system (DBTNS). Here, a comparative study is made on performance analysis of MAC unit using various non-conventional, non-binary number system. All the architecture is mapped on FPGA for analysis its performance.

Comparative performance analysis of FPGA-based MAC unit using non-conventional number system in TVL domain for signal processing algorithm

Today, the complication of binary digital hardware system is progressively growing. Due to this fact, new methodologies for efficiently describing and realising the digital systems are explored in this paper. Multi-valued logic methodology offers a few preferences over existing binary digital system. One of the well-known multi-valued logic systems is ternary value logic (TVL) system. It is seen that all kind of digital signal processing (DSP) algorithms widely use multiply-accumulate (MAC) operation for superior digital processing system. To implement high performance DSP algorithms MAC unit is used extensively. In current scenario, it is seen that non-conventional, non-binary number system-based architecture is also exhibited better performance. The example of such non-conventional, non-binary number systems is ternary residue number systems (TRNSs) and double base ternary number system (DBTNS). Here, a comparative study is made on performance analysis of MAC unit using various non-conventional, non-binary number system. All the architecture is mapped on FPGA for analysis its performance.

A modified discrete antlion optimizer for the ring star problem with secondary sub-depots

This paper introduces a new problem in the field of combinatorial optimization. This problem can be named as the ring star problem with secondary sub-depots (RSPSSD). RSPSSD has one fixed main depot, and it allows a network to be divided into three types of nodes, namely primary sub-depots (includes the main depot too), secondary sub-depots and left out nodes. The challenge of the problem is to select some primary and secondary sub-depots that minimize the total routing cost which has three components. The first one is the routing cost of the main circuit that covers all the primary sub-depots including the main depot. The second one is the total routing cost of all the secondary circuits, each of which covers a set of few secondary sub-depots and their nearest primary sub-depot. The secondary circuits also have a constraint on the number of secondary sub-depots in it. The last one is the assignment cost of the left out nodes to their nearest concentrators which is nothing but anyone from the main depot, primary or secondary sub-depots. The proposed RSPSSD problem is solved with the proposed modified discrete antlion optimizer and tested using some TSP benchmark instances. The random walk of an antlion and an ant is encoded with ternary number system. The statistical analysis and comparison of the result against some other algorithms are also presented. A real-life case study has also been shown to validate the proposed model and algorithm.

Balanced Number System

The article explores the application of binary and ternary number systems to three classical mathematical puzzles–weight problem of Bachet de Meziriac, binary numbers magic trick, and the detection of a counterfeit coin. The article further elucidates the generalization of these puzzles using the balanced number system.

Performance Analysis of FPGA Based MAC Unit using DBTNS Multiplier & TRNS Adder for Signal Processing Algorithm

Digital signal processing (DSP) algorithms are actually nothing but sum of product. So, they are computationally intensive. All the mathematical tasks related to DSP algorithm are based on multiplication and addition. So, the implementations of DSP algorithms-based applications extensively require multiplier and adder. Due to extensive use of multiplication and addition operation, speed up cannot be achieved. Designing the high-performance adder and multiplier are primary objective for implementing high performance signal processing applications. This hindrance can be removed by Multiply-Accumulate Unit (MAC). The special feature of a MAC unit is its ability to perform single cycle multiplication and addition operation.The performance of MAC Unit can be improved by using non-binary number system. Ternary value logic (TVL) has the ability to offer several advantages over conventional binary number system like reduce chip area, reduce overall delay. TVL can switch between three levels, such levels denoted by 0, 1, 2. As Residue Number Systems (RNS) can perform carry arithmetic operations, high performance adder can be implemented using RNS in TVL domain (TRNS). Partial product free multiplication can be implemented by using Double Base Number System in TVL domain (DBTNS). Double Base Ternary Number System (DBTNS) multiplier can perform better than conventional TVL multiplier. A MAC unit is used to perform the multiplication and accumulator operations together to avoid unnecessary overhead on the processor in terms of processing time and the on-chip memory requirements. Keeping in view of these issues, a new architecture is proposed for implementing high performance MAC unit for DSP applications. In this paper, a new approach of designing MAC unit is instigated using DBTNS multiplier and TRNS adder. A major bottleneck of implementing this architecture is the complexity involved in converting TVL to DBTNS in initial stage and converting TRNS to TVL in final stage. The performance of Ternary Residue Number Systems (TRNS) system depends on selection of moduli because selection of moduli is not properly maintained then it will affect system speed, dynamic range and hardware complexity. Proposed MAC unit is mapped on field programmable gate array (FPGA) for analysis its performance.

FPGA Implementation of MAC Unit for Double Base Ternary Number System (DBTNS) and its Performance Analysis

FPGA Implementation of MAC Unit for Double Base Ternary Number System (DBTNS) and its Performance Analysis

Combined Balanced Ternary Number System: An Approach to a New Computational Number System combining The Ternary Number System and the Balanced Ternary Number System in the field of Computational Mathematics

Combined Balanced Ternary Number System: An Approach to a New Computational Number System combining The Ternary Number System and the Balanced Ternary Number System in the field of Computational Mathematics

Ternary number systems in finite fields

The work continues the author's previous study of positional number systems in finite fields. The paper considers ternary number systems and arithmetic operations algorithms for the representation of elements of finite fields in the so-called ternary reduced number systems, which are reductions of the canonical number systems when mapping the corresponding ring of integers of a quadratic field into some prime field. A classification of finite fields in which such number systems exist is given. It is proved that the reduced ternary number systems exist for most finite prime fields.

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic.

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.

NUMBER SYSTEMS PERTAINING TO EUCLIDEAN RINGS OF IMAGINARY QUADRATIC INTEGERS

Abstract. For a ring R of imaginary quadratic integers, using a conceptof a unitary number system in place of the Motzkin’s universal side divisor,we show that the following statements are equivalent:(1) R is Euclidean.(2) R has a unitary number system.(3) R is norm-Euclidean.Through an application of the above theorem we see that R admits binaryor ternary number systems if and only if R is Euclidean. 1. IntroductionIt is well known that among rings of imaginary quadratic integers, only nineringsZp 1; Zp 2; Z1 +p 32; Z1 + 72; Z1 +p 112;Z1 +p 192; Z1 +p 432; Z1 +p 672; Z1 +p 1632are principal ideal domains, which was conjectured by Gauss and settled com-pletely by Stark [15]. Furthermore, only the rst ve examples of those are Eu-clidean domains, whose Euclidean functions are induced by the norms; whereas,the other four have no Euclidean functions whatsoever. A brilliant proof for thelatter claim was presented by Motzkin [12] around 1949, who came up with acriterion for an integral domain to be Euclidean. But the proof seems too tersefor laymen. And lling details of Motzkin’s proof especially for non-existence ofEuclidean algorithm of ring Zh

Model of Digital Image Attributed with Virtual Memory Basing on Pseudo–Ternary Number System

A model of digital image attributed with virtual memory by analogy with computer memory is developed. In addition to operation of storage element reset the fixation (weaving) operation of virtual storage element is defined. The basic model image representations are described and their practical interpretations are discussed.

Classification of ternary quasicanonical number systems in imaginary quadratic fields and their application

In this paper all possible ternary quasicanonical number system in imaginary quadratic fields are considered. For representation of algebraic integers of imaginary quadratic fields in the specified number systems an algorithm based on the division with remainder is used. In addition, the algorithms of the basic arithmetic operations in ternary number systems in the ring of Eisenstain integers are synthesized. Method of fast error-free cyclic convolution computation is considered.

PROPERTIES OF HYPERHOLOMORPHIC FUNCTIONS ON DUAL TERNARY NUMBERS

We research properties of ternary numbers with values in <TEX>${\Lambda}(2)$</TEX>. Also, we represent dual ternary numbers in the sense of Clifford algebras of real six dimensional spaces. We give generation theorems in dual ternary number systems in view of Clifford analysis, and obtain Cauchy theorems with respect to dual ternary numbers.

Regular Functions with Values in Ternary Number System on the Complex Clifford Analysis

We define a new modified basis which is an association of two bases, and . We give an expression of the form , where is a real number and is a complex number on three-dimensional real skew field. And we research the properties of regular functions with values in ternary field and reduced quaternions by Clifford analysis.

Automaton implementations of the process of generating a Collatz sequence

Algorithms for producing a Collatz sequence are considered in the cases of the binary and ternary number systems. Advantages of this approach to the representation of such a sequence are considered. Logic circuits of iterative automata that implement the algorithms described are presented.