Ternary Digital System Research Articles

Simplification of Ternary Function using Variable Entered Mapping Technique

This paper describes the steps for minimization of ternary function i.e. three level logic using variable entered mapping technique. Here we applied VEM technique successfully to the ternary function and result is verified using truth table of given ternary equations. We also implemented simplified expression using decoder and ternary gates as well as using ternary multiplexer. It will be more difficult as radix of the number system increases to get more difficult in minimization and to design circuit. In this paper we successfully applied VEM technique to ternary system, the proposed technique is developed for the ternary logic function simplification. It incorporates all designed rules for ternary logic system design and gives the output in the form of Sum-of-Product (SOP) terms. Generally VEM technique is used for the minimization of binary function so the rule used here are different than binary logic. Output equation of ternary digital system is in the form of F = F2 + 1. (F1) Where, F2 = 2‟s minterms and F1 = 1‟s minterms.

Minimization of Multiple Value function using Quine Mc-Cluskey Technique

This paper presents minimization technique for multiple value function using Quine Mc-cluskey‟s method. This paper provide steps for the minimization of multivalued function i.e. radix >2 digital system. The ternary digital system which radix=3 is considered here minimized function of MVL function implemented using decoder and multiplexer and answer is verified using ternary k-map. As the radix of system increases, the difficulties in the minimization or reduction of logic function is get increases. It becomes difficult to for higher radix to reduce the function design equation. In this paper we successfully applied Quine Mc-Cluskey‟s technique to ternary system. In this paper simplified expression designed using decoder and ternary gate. Same expression implemented using ternary multiplexer. Hardware required for both cases is evaluated. It incorporates all designed rules for ternary logic system design and gives the output in the form of Sum-of-Product (SOP) terms.

A Cyclic Algebra for the Synthesis of Ternary Digital Systems

The original multivalued algebra defined by Post in 1921 [1] included the cyclization operation in its generating set. Up to now the algebra has not been used for the synthesis of ternary digital systems because of two shortcomings: no simple canonical forms are possible, and the cyclization is difficult to implement.

Threshold Synthesis of Ternary Digital Systems

This paper presents a synthesis method of ternary digital systems by means of a threshold algebra. The method is based on the fact that the K operations of any ternary function can be expressed as threshold operations on a set of functions called midterms. Such midterms can be easily generated from the outputs of the ternary multivibrators described by the authors in a previous paper [4]. The Quine method is extended to the minimization of ternary threshold normal forms. RTL circuits implementing the operations are described, and the threshold design of a fast carry propagation ternary adder is outlined in order to illustrate the method.

Synchronizing Sequences for Incompletely Specified Flow Tables

This paper presents a synthesis method of ternary digital systems by means of a threshold algebra. The method is based on the fact that the K operations of any ternary function can be expressed as threshold operations on a set of functions called midterms. Such midterms can be easily generated from the outputs of the ternary multivibrators described by the authors in a previous paper [4].