Simplification of Ternary Function using Variable Entered Mapping Technique

Abstract

This paper describes the steps for minimization of ternary function i.e. three level logic using variable entered mapping technique. Here we applied VEM technique successfully to the ternary function and result is verified using truth table of given ternary equations. We also implemented simplified expression using decoder and ternary gates as well as using ternary multiplexer. It will be more difficult as radix of the number system increases to get more difficult in minimization and to design circuit. In this paper we successfully applied VEM technique to ternary system, the proposed technique is developed for the ternary logic function simplification. It incorporates all designed rules for ternary logic system design and gives the output in the form of Sum-of-Product (SOP) terms. Generally VEM technique is used for the minimization of binary function so the rule used here are different than binary logic. Output equation of ternary digital system is in the form of F = F2 + 1. (F1) Where, F2 = 2‟s minterms and F1 = 1‟s minterms.