Ternary Content Addressable Memory Cell Research Articles

Ternary Content-Addressable Memory Based on a Single Two-Dimensional Transistor for Memory-Augmented Learning.

Ternary content-addressable memory (TCAM) is promising for data-intensive artificial intelligence applications due to its large-scale parallel in-memory computing capabilities. However, it is still challenging to build a reliable TCAM cell from a single circuit component. Here, we demonstrate a single transistor TCAM based on a floating-gate two-dimensional (2D) ambipolar MoTe2 field-effect transistor with graphene contacts. Our bottom graphene contacts scheme enables gate modulation of the contact Schottky barrier heights, facilitating carrier injection for both electrons and holes. The 2D nature of our channel and contact materials provides device scaling potentials beyond silicon. By integration with a floating-gate stack, a highly reliable nonvolatile memory is achieved. Our TCAM cell exhibits a resistance ratio larger than 1000 and symmetrical complementary states, allowing the implementation of large-scale TCAM arrays. Finally, we show through circuit simulations that in-memory Hamming distance computation is readily achievable based on our TCAM with array sizes up to 128 cells.

CMOS-Integrated Ternary Content Addressable Memory using Nanocavity CBRAMs for High Sensing Margin.

The development of data-intensive computing methods imposes a significant load on the hardware, requiring progress toward a memory-centric paradigm. Within this context, ternary content-addressable memory (TCAM) can become an essential platform for high-speed in-memory matching applications of large data vectors. Compared to traditional static random-access memory (SRAM) designs, TCAM technology using non-volatile resistive memories (RRAMs) in two-transistor-two-resistor (2T2R) configurations presents a cost-efficient alternative. However, the limited sensing margin between the match and mismatch states in RRAM structures hinders the potential of using memory-based TCAMs for large-scale architectures. Therefore, this study proposes a practical device engineering method to improve the switching response of conductive-bridge memories (CBRAMs) integrated with existing complementary metal-oxide-semiconductor (CMOS) transistor technology. Importantly, this work demonstrates a significant improvement in memory window reaching 1.87 × 107 by incorporating nanocavity arrays and modifying electrode geometry. Consequently, TCAM cells using nanocavity-enhanced CBRAM devices can exhibit a considerable increase in resistance ratio up to 6.17 × 105, thereby closely approximating the sensing metrics observed in SRAM-based TCAMs. The improved sensing capability facilitates the parallel querying of extensive data sets. TCAM array simulations using experimentally verified device models indicate a substantial sensing margin of 65× enabling a parallel search of 2048 bits.

Ferroelectric Hafnia-Based M3D FeTFTs Annealed at Extremely Low Temperatures and TCAM Cells for Computing-in-Memory Applications.

In order to overcome the bottleneck between the central processor unit and memory as well as the issue of energy consumption, computing-in-memory (CIM) is becoming more popular as an alternative to the traditional von Neumann structure. However, as artificial intelligence advances, the networks require CIM devices to store billions of parameters in order to handle huge data traffic demands. Monolithic three-dimensional (M3D) stacked ferroelectric thin-film transistors (FeTFTs) are one of the promising techniques for realizing high-density CIM devices that can store billions of parameters. In particular, oxide channel-based FeTFTs are well suited for these applications due to low-temperature processes, nonvolatility, and 3D integration capability. Nevertheless, the M3D-integrated CIM devices including hafnia ferroelectric films need the high-temperature annealing process to crystallize the ferroelectric layer, making M3D integration difficult. When the FeTFTs are fabricated with an M3D structure, the high-temperature process causes thermal issues in the underlying devices. Here, we present the focused microwave annealed (FMA) oxide FeTFTs with M3D integration at a low temperature of 250 °C. We confirmed that the FeTFTs with metal-ferroelectric-metal-insulator-semiconductor structure exhibited a large memory window of 3.2 V, good endurance over 106 cycles, and a long retention time of 105 s. To understand the different electrical characteristics of FeTFTs in the top and bottom layers, we experimentally analyzed the density of the state of the oxide channel and ferroelectric properties of the ferroelectric gate insulator by using multifrequency capacitance-voltage measurement and nucleation-limited-switching model analysis, respectively. With our approach, we demonstrate for the first time a vertical stacked FeTFTs-based ternary-content-addressable memory (TCAM) cell for CIM application. We believe that the proposed M3D-stacked TCAM cells composed of FeTFTs can be used in high-density memory, energy-efficient memory, and CIM technology.

Ferroelectric-gate tunnel field-effect transistor one-transistor ternary contents addressable memory

In the era of ‘big data’, the von Neumann architecture has significant energy consumption and latency penalties for data transfer between memory and processor. However, ternary content addressable memories (TCAMs) enable fast and energy-efficient operation by performing a parallel search for given data and returning information about whether it matches. In this study, a single transistor (1T) ferroelectric-gate tunnel FET (FeTFET) was introduced for TCAM operations, and its functionality was verified through technology computer-aided design (TCAD) simulations. The FeTFET has intrinsic directional currents due to its unique p–i–n structure. Also, the transfer curve of the FeTFET can be shifted in both directions depending on the polarization state of the ferroelectric material. By combining these properties of the FeTFET, it was confirmed that stable search operations can be performed for stored logic states. Thus, compared to conventional TCAM cell that use two or more transistors, it is expected that the proposed 1T-TCAM cell can store and search more bits in the same area.

Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme

Fast communication between networking devices increases the importance of the ternary content addressable memory (TCAM). The demands for low energy in networking devices have accelerated the research on nonvolatile TCAMs that store data without the power supply. Recently, ferroelectric field-effect transistors (FeFETs), nonvolatile three-terminal devices with a high on/off ratio, have been adopted for TCAMs. Although the previous FeFET TCAMs consume low write energy with a significantly compact TCAM cell area, they suffer from write problems: 1) the write scheme cannot afford the saturated polarization switching in FeFETs and 2) the states stored in the unselected TCAM cells are changed during the write operation. In addition, search yield is deteriorated by wide process variations of FeFETs. This paper proposes a novel FeFET TCAM that is free from the write problems of the previous FeFET TCAMs and tolerant to process variations. This paper also proposes a novel match line scheme to improve search energy and time by reducing match line capacitance and the amount of discharged voltage in the match evaluation phase. Industrial-compatible 28 nm technology-based simulation results with the Preisach FeFET model show that the proposed FeFET TCAM achieves the highest search yield.

Design of a Compact Spin-Orbit-Torque-Based Ternary Content Addressable Memory

This article presents the design of a novel and compact spin-orbit torque (SOT)-based ternary content addressable memory (TCAM). Experimentally validated/calibrated micromagnetic and macrospin simulations have been used to quantify various tradeoffs regarding the write operation, such as write energy, error rate, and retention time. SPICE simulations incorporating various sources of variability are used to evaluate search operations, optimize the proposed novel TCAM cell based on SOT magnetic random access memory (SOT-MRAM), and benchmark it against static random access memory (SRAM)- and FeFET-based TCAMs. We show low search error rates (SERs) (< 10−4) while considering various sources of variability for four transistors- and two magnetic tunnel junctions (MTJs)-based TCAM array.

Ultradense One-Memristor Ternary-Content-Addressable Memory Based on Ferroelectric Diodes

In this Letter, for the first time, one-memristor (1M)-based ternary-content-addressable memory (TCAM) with an ultradense 4F2 cell area is proposed on a single reconfigurable TiN/hafnium zirconium oxide (HZO)/indium gallium zinc oxide (IGZO)/TiN ferroelectric (FE) diode. By modulating the FE-polarization-controlled Schottky junction that exists at the interface, reconfigured P–N, N–P, and ohmic like junctions of the FE diodes were designed for ‘0’, ‘1’, and ‘X’ storage states in the TCAM cell, respectively. In addition to non-volatile FE polarization for data storage, ambipolar-like behavior induced by the symmetrical junction characteristics was obtained on the diodes for searching queries. Using both non-volatile and ambipolar-like characteristics, typical TCAM functions with a maximum driving on/off ratio of ~500 were confirmed experimentally on a single FE diode, indicating the great potential of this memory device in area-efficient artificial intelligence processors.

Computational Associative Memory with Amorphous Metal‐Oxide Channel 3D NAND‐Compatible Floating‐Gate Transistors (Adv. Electron. Mater. 12/2022)

Massively Scalable Ternary Content-Addressable Memories In article number 2200643, Xunzhao Yin, Xiao Gong, and co-workers present high-performance floating-gate transistors with an amorphous-InGaZnO channel and the application in ternary content addressable memories (TCAMs). The two-transistor configuration and the extremely low OFF current of the TCAM cell significantly improve the scalability of the TCAM array.

High-Speed Memristive Ternary Content Addressable Memory

This article presents an ultra-high-speed memristor-based non-volatile Ternary Content Addressable Memory (TCAM) for use in real-time and big-data applications that require low power dissipation and fast data retrieval. It proposes a novel memristive TCAM (MTCAM) cell using memristors as a bit storage device along with an ultra-fast match line sense amplifier to minimize search time. SPICE simulation on 45 nm technology show that the search delay on a 144-bit proposed MTCAM at a supply voltage of 1 V and a sense margin of 140 mV is 175 ps with per bit search energy of 1.2 fJ. It is 1.12× times faster and dissipates 67 percent less search energy per bit than the fastest existing 144-bit MTCAM design.

Gate All around CNTFET based Ternary Content Addressable Memory

This paper proposes a design of gate all around CNTFET based ternary content addressable memory (TCAM). TCAM cell is designed and simulated in HSPICE using top gated CNTFET (TG-CNTFET) & gate all around CNTTFET (GAA-CNTFET). Dual chirality technique is used to design TCAM cell i.e. different chirality for n-type CNTFET & p-type CNTFET which utilizes different threshold voltages and hence improve the performance. Comparative analysis has been done for various parameters viz. Static noise margin (SNM), delay, power and power delay product (PDP). It has been found that GAA-CNTFET based TCAM gives better SNM and power as compared to TG-CNTFET based TCAM, however TG-CNTFET based TCAM gives less delay. However overall PDP is less in GAA-CNTFET which make is suitable for circuit applications as compared to TG-CNTFET.

A skyrmion content-addressable cell for skyrmion magnetic memories

Content-addressable memories (CAMs) allow searching a pattern, processing in parallel all the data stored. Beyond-CMOS technologies can provide new opportunities to improve CAM memories implementations both at the device and architectural level. In this article, we propose a ternary content-addressable memory cell based on skyrmion technology. The proposed memory cell is based on skyrmion racetrack memory. The cell is able to signal if the bit contained in the cell in form of skyrmion corresponds to an electrical input, the target of the search operation. The proposed design, verified by means of micromagnetic simulations, has an area of 0.054 μm2 and can perform a search operation in 3.3 ns with an energy of 10.5 fJ. The operation performed is non-destructive and does not require conversion between the magnetic and the electronic domains. For this reason, the designed cell has the potential to be used as a basic block for non-volatile CAM memories. Here, we propose also a layout structure to implement a CAM memory employing the proposed cell. This structure allows to achieve memory density comparable to traditional racetrack memories and execute at the same time CAM operations.

The Effect of DTMOS Transistors on the Performance of a Memristor-based Ternary CAM Cell in Low Power Applications

The Effect of DTMOS Transistors on the Performance of a Memristor-based Ternary CAM Cell in Low Power Applications

Design of low-power and high-speed CNTFET-based TCAM cell for future generation networks

In network routers and lookup tables for fast searching, ternary content addressable memories (TCAMs) have found great use. For future generation networks, architecture is essential for efficient TCAM in terms of power consumption and speed of service. A TCAM cell with an optimized CNTFET is proposed in this paper. The TCAM cell proposed is designed for improved performance using optimized CNTFET with shorted gate (SG) CNTFET and independent gate CNTFET (IG-CNTFET). As access transistors, IG-CNTFETs are used in the SRAM cell design, and SG-CNTFETs are used in the comparison circuit. The 4 × 4 TCAM array was also planned using the TCAM cells proposed. The suggested CNTFET TCAM cell and array showed better performance than that of TCAM cells and arrays based on CMOS and FinFET. The suggested CNTFET-based TCAM with SG shows a substantial improvement in search delay and average power and peak power compared to CMOS and FinFET-based cell technology. Compared to CMOS and FinFET technologies, the average capacity of the proposed TCAM cell is substantially enhanced. The proposed technique's search delay is enhanced by 17.2 percent over TCAM cell based on FinFET. Compared to the FinFET and CMOS-based TCAM cell, the peak power of the proposed technique is also enhanced. All the simulations are carried out at 32 nm with HSPICE technology.

A N ovel NOR Type TCAM Deploy D ual V T cell with OR Type Cascade Match Line Structure

We look over improvements in the schemes of large size content addressable memory (CAM). A CAM is a very important device that executes the routing table function within a single clock cycle in network router to transmit information over the network. CAMs are particularly popular in network switches to classify and sending information packets, they are also helpful in other different applications that require fast information retrieval from routing table. The primary CAM configuration challenge is to decrease power dissipation related with the lot of parallel activity in memory circuitry during search operation. As innovation going on in technology scaling, it continues minimizing the dynamic power dissipation of CAMs, however it also rises the leakage current of transistors. Thus, the static power is turning into a noteworthy bit of the whole power dissipation in CAMs. Here, we introduced a procedure which advantageous for high capacity Ternary Content Addressable Memory (TCAM) that minimize the static power dissipation in SRAM storage cell part and speed up activity in searching part of TCAM cell. We also divide whole memory into equivalent segments which improve performance of our design. We examine the different schemes and introduced the trade-offs of applying the techniques. Simulation and design have done by using Tanned EDA V.16 tool. For recreations of Low power TCAM structures we utilized predictive technology model (PTM) 45nm for high performance (HP) and low power (LP), which incorporate metal gate, high-k and stress effect of CMOS technology.

Ferroelectric ternary content-addressable memory for one-shot learning

Deep neural networks are efficient at learning from large sets of labelled data, but struggle to adapt to previously unseen data. In pursuit of generalized artificial intelligence, one approach is to augment neural networks with an attentional memory so that they can draw on already learnt knowledge patterns and adapt to new but similar tasks. In current implementations of such memory augmented neural networks (MANNs), the content of a network’s memory is typically transferred from the memory to the compute unit (a central processing unit or graphics processing unit) to calculate similarity or distance norms. The processing unit hardware incurs substantial energy and latency penalties associated with transferring the data from the memory and updating the data at random memory addresses. Here, we show that ternary content-addressable memories (TCAMs) can be used as attentional memories, in which the distance between a query vector and each stored entry is computed within the memory itself, thus avoiding data transfer. Our compact and energy-efficient TCAM cell is based on two ferroelectric field-effect transistors. We evaluate the performance of our ferroelectric TCAM array prototype for one- and few-shot learning applications. When compared with a MANN where cosine distance calculations are performed on a graphics processing unit, the ferroelectric TCAM approach provides a 60-fold reduction in energy and 2,700-fold reduction in latency for a single memory search operation. A compact ternary content-addressable memory cell, which is based on two ferroelectric field-effect transistors, can provide memory augmented neural networks with improved energy and latency performance compared with traditional approaches based on graphics processing units.

A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier

Ternary content-addressable memory (TCAM) is limited by large cell area, high search power, significant active-mode leakage current, and a tradeoff between search speed and signal margin on the match-line (ML). In this paper, we developed a split-controlled single-load 14T (SCSL-14T) TCAM cell and a triple-margin voltage sense amplifier (TM-VSA) to achieve the following: 1) compact cell area; 2) lower search delay and search energy; 3) reduced current leakage in standby and active modes; and 4) tolerance for small sensing margin. A testchip with 320-Kb 14T-TCAM macro was fabricated using a 28-nm CMOS logic process and modified compact foundry six-transistor (6T) cell. The proposed macro achieved search delay of only 710 ps and 0.422 fJ/bit/search.

Dual-chirality GAA-CNTFET-based SCPF-TCAM cell design for low power and high performance

Ternary content-addressable memory (TCAM) is a type of associative memory used in many applications for high-speed data searching. We present herein a gate-all-around (GAA) carbon nanotube field-effect transistor (CNTFET)-based self-controlled TCAM cell design with a precharge-free match line. We compare the power–delay product (PDP) and static noise margin between the GAA-CNTFET-based traditional and proposed TCAM cell designs at the 11-nm technology node with a supply voltage of 0.8 V. The simulations are performed using the Virtuoso tool for different parameter values with the Stanford University GAA-CNTFET model. The simulation results show that, compared with the traditional design, the proposed design exhibits a significant reduction in power by 51.30%, delay by 17.16%, and PDP by 59.66% for a chiral vector of (20, 16, 0) with two channels. It is observed that the best chirality for the proposed design is (14, 20, 0) for a single channel, but (16, 16, 0) and (20, 16, 0) for a dual channel in terms of power, delay, stability, and PDP.

Compact and Low Power 11T-2MTJ Non-Volatile Ternary Content Addressable Memory Cell with High Sense Margin

Compact and Low Power 11T-2MTJ Non-Volatile Ternary Content Addressable Memory Cell with High Sense Margin

Ternary content-addressable memory with MoS2 transistors for massively parallel data search

Ternary content-addressable memory (TCAM) is specialized hardware that can perform in-memory search and pattern matching for data-intensive applications. However, achieving TCAMs with high search capacity, good area efficiency and good energy efficiency remains a challenge. Here, we show that two-transistor–two-resistor (2T2R) transition metal dichalcogenide TCAM (TMD-TCAM) cells can be created by integrating single-layer MoS2 transistors with metal-oxide resistive random-access memories (RRAMs). The MoS2 transistors have very low leakage currents and can program the RRAMs with exceptionally robust current control, enabling the parallel search of very large numbers of data bits. These TCAM cells also exhibit remarkably large resistance ratios (R-ratios) of up to 8.5 × 105 between match and mismatch states. This R-ratio is comparable to that of commercial TCAMs using static random-access memories (SRAMs), with the key advantage that our 2T2R TCAMs use far fewer transistors and have zero standby power due to the non-volatility of RRAMs. By integrating two-dimensional MoS2 transistors with metal-oxide resistive random-access memories, two-transistor–two-resistor ternary content-addressable memory cells can be created, which could be used to search large amounts of data in parallel.

Memristor TCAMs Accelerate Regular Expression Matching for Network Intrusion Detection

We propose memristor-based TCAMs (Ternary Content Addressable Memory) circuits to accelerate Regular Expression (RegEx) matching through in memory processing of finite automata. RegEx matching is a key function in network security to find malicious actors. However, RegEx matching latency and power can be incredibly high and current proposals are challenged to perform wire-speed matching for large rulesets. Our approach dramatically decreases operating power, enables high throughput, and the use of nanoscale memristor TCAM circuits (mTCAMs) enables compression techniques to expand rulesets. We fabricated and demonstrated nanoscale memristor TCAM cells. SPICE simulations investigate performance at scale and a mTCAM dynamic power model using 16 nm layout parameters demonstrates ~0.2 fJ/bit/search energy for a 36 × 250 mTCAM array. A tiled architecture is proposed to implement a Snort ruleset and assess application performance. Compared to a state-of-the-art FPGA approach (2 Gbps, ~1 W), we show ×4 throughput (8 Gbps) at 55% the power (0.55 W) without standard TCAM power-saving techniques. Our performance comparison improves further when striding (searching multiple characters at once) is considered, resulting in 47.2 Gbps at 1.2 W for our approach compared to 3.9 Gbps at 630 mW for strided FPGA NFA, demonstrating a promising path to wire-speed RegEx matching on large scale rulesets.