Ternary Content Addressable Memory Research Articles

Semantic memory-based dynamic neural network using memristive ternary CIM and CAM for 2D and 3D vision.

The brain is dynamic, associative, and efficient. It reconfigures by associating the inputs with past experiences, with fused memory and processing. In contrast, AI models are static, unable to associate inputs with past experiences, and run on digital computers with physically separated memory and processing. We propose a hardware-software co-design, a semantic memory-based dynamic neural network using a memristor. The network associates incoming data with the past experience stored as semantic vectors. The network and the semantic memory are physically implemented on noise-robust ternary memristor-based computing-in-memory (CIM) and content-addressable memory (CAM) circuits, respectively. We validate our co-designs, using a 40-nm memristor macro, on ResNet and PointNet++ for classifying images and three-dimensional points from the MNIST and ModelNet datasets, which achieves not only accuracy on par with software but also a 48.1 and 15.9% reduction in computational budget. Moreover, it delivers a 77.6 and 93.3% reduction in energy consumption.

Ternary Content-Addressable Memory Based on a Single Two-Dimensional Transistor for Memory-Augmented Learning.

Ternary content-addressable memory (TCAM) is promising for data-intensive artificial intelligence applications due to its large-scale parallel in-memory computing capabilities. However, it is still challenging to build a reliable TCAM cell from a single circuit component. Here, we demonstrate a single transistor TCAM based on a floating-gate two-dimensional (2D) ambipolar MoTe2 field-effect transistor with graphene contacts. Our bottom graphene contacts scheme enables gate modulation of the contact Schottky barrier heights, facilitating carrier injection for both electrons and holes. The 2D nature of our channel and contact materials provides device scaling potentials beyond silicon. By integration with a floating-gate stack, a highly reliable nonvolatile memory is achieved. Our TCAM cell exhibits a resistance ratio larger than 1000 and symmetrical complementary states, allowing the implementation of large-scale TCAM arrays. Finally, we show through circuit simulations that in-memory Hamming distance computation is readily achievable based on our TCAM with array sizes up to 128 cells.

Enhanced CPU Design for SDN Controller.

Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compared to other transistor technologies regarding energy efficiency and circuit speed. To the best of our knowledge, this is the first time that a ternary design has been applied inside the CPU of an SDN controller. Earlier studies focused on Ternary Content-Addressable Memory (TCAM) in SDN. This paper proposes a new 1-trit Ternary Full Adder (TFA) to decrease the propagation delay and the Power-Delay Product (PDP). The proposed design is compared to the latest 17 designs, including 15 designs that are 1-trit TFA CNTFET-based, 2-bit binary FA FinFET-based, and 2-bit binary FA CMOS-based, using the HSPICE simulator, to optimize the CPU utilization in SDN environments, thereby enhancing programmability. The results show the success of the proposed design in reducing the propagation delays by over 99% compared to the 2-bit binary FA CMOS-based design, over 78% compared to the 2-bit binary FA FinFET-based design, over 91% compared to the worst-case TFA, and over 49% compared to the best-case TFAs.

CMOS-Integrated Ternary Content Addressable Memory using Nanocavity CBRAMs for High Sensing Margin.

The development of data-intensive computing methods imposes a significant load on the hardware, requiring progress toward a memory-centric paradigm. Within this context, ternary content-addressable memory (TCAM) can become an essential platform for high-speed in-memory matching applications of large data vectors. Compared to traditional static random-access memory (SRAM) designs, TCAM technology using non-volatile resistive memories (RRAMs) in two-transistor-two-resistor (2T2R) configurations presents a cost-efficient alternative. However, the limited sensing margin between the match and mismatch states in RRAM structures hinders the potential of using memory-based TCAMs for large-scale architectures. Therefore, this study proposes a practical device engineering method to improve the switching response of conductive-bridge memories (CBRAMs) integrated with existing complementary metal-oxide-semiconductor (CMOS) transistor technology. Importantly, this work demonstrates a significant improvement in memory window reaching 1.87 × 107 by incorporating nanocavity arrays and modifying electrode geometry. Consequently, TCAM cells using nanocavity-enhanced CBRAM devices can exhibit a considerable increase in resistance ratio up to 6.17 × 105, thereby closely approximating the sensing metrics observed in SRAM-based TCAMs. The improved sensing capability facilitates the parallel querying of extensive data sets. TCAM array simulations using experimentally verified device models indicate a substantial sensing margin of 65× enabling a parallel search of 2048 bits.

Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices.

Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memory (LiM) computing applications. In this paper, we analyze the temperature-dependent device and circuit characteristics of the floating gate field effect transistor (FGFET) source drain barrier (SDB) and FGFET central shallow barrier (CSB) identified in previous papers, and their applicability to LiM applications is specifically confirmed. These FGFETs have the advantage of being much more compatible with existing silicon-based complementary metal oxide semiconductor (CMOS) processes compared to devices using new materials such as ferroelectrics for LiM computing. Utilizing the 32 nm technology node, the leading-edge node where the planar metal oxide semiconductor field effect transistor structure is applied, FGFET devices were analyzed in TCAD, and an environment for analyzing circuits in HSPICE was established. To seamlessly connect FGFET-based devices and circuit analyses, compact models of FGFET-SDB and -CSBs were developed and applied to the design of ternary content-addressable memory (TCAM) and full adder (FA) circuits for LiM. In addition, depression and potential for application of FGFET devices to neural networks were analyzed. The temperature-dependent characteristics of the TCAM and FA circuits with FGFETs were analyzed as an indicator of energy and delay time, and the appropriate number of CSBs should be applied.

An Effective Selection of Memory Technologies for TCAM to Improve the Search Operations: Demonstration of Memory Efficiency in SDN Recovery

Ternary Content-Addressable Memory (TCAM) is used for storing the flow tables in software-defined networking (SDN)-based OpenFlow switches. However, the TCAM can store only a certain number of flow tables (8000). Moreover, when the switch flow tables need to be updated due to the link failure in the SDN, further updates may be lost due to the flow tables limit of the TCAM space. Hence, to resolve this issue, other memories need to be used in conjunction with TCAM to enhance the memory operations of TCAM. When considering which flash memory technology is to be used in conjunction with TCAM, we need to balance several factors to ensure optimal performance, speed, endurance, reliability, integration complexity, and cost-effectiveness. Hence, it leads to a multi-criteria decision-making problem regarding the selection of other memory technologies such as 3D XPoint, Magnetoresistive RAM, Resistive RAM, and Ferroelectric RAM. In this paper, we use the analytical network process (ANP) method to select the suitable technology in conjunction with TCAM, considering the features of the memory technologies for Software-Defined Internet-of-Things (SD-IoT). We provide a comprehensive numerical model leveraging the ANP to rank the memory technologies regarding their weights. The highest weights identify the most suitable technology for TCAM. We perform simulations to show the effectiveness of the mathematical model utilizing the ANP. The results show that the suggested methodology reduces the recovery delay, improves the packets received ratio (PRR), decreases the jitter, and increases the throughput.

One-Transistor Ternary Content-Addressable Memory Based on Localized Ferroelectric Switching for Massive and Accurate Routing

One-Transistor Ternary Content-Addressable Memory Based on Localized Ferroelectric Switching for Massive and Accurate Routing

Flow-based Service Time optimization in software-defined networks using Deep Reinforcement Learning

A Ternary Content-Addressable Memory (TCAM) constitutes a memory variant employed within Software Defined Networking (SDN) node flow tables. These TCAMs deliver swift processing, enabling rapid parallel lookups. Nonetheless, due to their high energy consumption and cost, TCAMs have limited dimensions. This size constraint influences rule capacity, and suboptimal rule management can degrade network quality of service. Although different techniques for flow table management have been proposed during recent years, such as eviction, idle and hard timeout mechanisms, this paper proposes a Deep-Reinforcement Learning (DRL) solution, namely DRL-Idle, that is able to maximize the service time of the flows in an SDN network without considering any assumption about their status throughout time. By means of a continuous learning, DRL-Idle is able to also minimize the number of rule installations that are required to serve the target flows. Based on the idea of dynamically modifying the idle timeout value of the flows according to their needs, DRL-Idle outperforms existing approaches aiming at solving the Rule Placement Problem, averaging a 30% increase in performance.

CMOS-RRAM Based Non-Volatile Ternary Content Addressable Memory (nvTCAM)

CMOS-RRAM Based Non-Volatile Ternary Content Addressable Memory (nvTCAM)

Monolithic three-dimensional integration of RRAM-based hybrid memory architecture for one-shot learning

In this work, we report the monolithic three-dimensional integration (M3D) of hybrid memory architecture based on resistive random-access memory (RRAM), named M3D-LIME. The chip featured three key functional layers: the first was Si complementary metal-oxide-semiconductor (CMOS) for control logic; the second was computing-in-memory (CIM) layer with HfAlOx-based analog RRAM array to implement neural networks for feature extractions; the third was on-chip buffer and ternary content-addressable memory (TCAM) array for template storing and matching, based on Ta2O5-based binary RRAM and carbon nanotube field-effect transistor (CNTFET). Extensive structural analysis along with array-level electrical measurements and functional demonstrations on the CIM and TCAM arrays was performed. The M3D-LIME chip was further used to implement one-shot learning, where ~96% accuracy was achieved on the Omniglot dataset while exhibiting 18.3× higher energy efficiency than graphics processing unit (GPU). This work demonstrates the tremendous potential of M3D-LIME with RRAM-based hybrid memory architecture for future data-centric applications.

Flash-based content addressable memory with L2 distance for memory-augmented neural network

Memory-augmented neural network (MANN) has received increasing attention as a promising approach to achieve lifelong on-device learning, of which implementation of the explicit memory is vital. Content addressable memory (CAM) has been designed to accelerate the explicit memory by harnessing the in-memory-computing capability. In this work, a CAM cell with quadratic code is proposed, and a 1Mb Flash-based multi-bit CAM chip capable of computing Euclidean (L2) distance is fabricated. Compared with ternary CAM, the latency and energy are significantly reduced by 5.3- and 46.6-fold, respectively, for the MANN on Omniglot dataset. Besides, the recognition accuracy has slight degradation (<1%) even after baking for 105 s at 200°C, demonstrating the robustness to environmental disturbance. Performance evaluation indicates a reduction of 471-fold in latency and 1267-fold in energy compared with GPU for search operation. The proposed robust and energy-efficient CAM provides a promising solution to implement lifelong on-device machine intelligence.

Multiplexing in photonics as a resource for optical ternary content-addressable memory functionality

Abstract In this paper, we combine a Content-Addressable Memory (CAM) encoding scheme previously proposed for analog electronic CAMs (E-CAMs) with optical multiplexing techniques to create two new photonic CAM architectures—wavelength-division multiplexing (WDM) optical ternary CAM (O-TCAM) and time-division multiplexing (TDM) O-TCAM. As an example, we show how these two O-TCAM schemes can be implemented by performing minor modifications in microring-based silicon photonic (SiPh) circuits originally optimized for exascale interconnects. Here, our SiPh O-TCAM designs include not only the actual search engine, but also the transmitter circuits. For the first time, we experimentally demonstrate O-TCAM functionality in SiPh up to ∼ 4 Gbps ${\sim} 4\,\,\text{Gbps}$ and we prove in simulation feasibility for speeds up to 10 Gbps, 10 times faster than typical E-TCAMs at the expense of higher energy consumption per symbol of our O-TCAM Search Engine circuits than the corresponding E-TCAMs. Finally, we identify which hardware and architecture modifications are required to improve the O-CAM’s energy efficiency towards the level of E-CAMs.

Ensuring reliable network operations and maintenance: The role of PMRF for switch maintenance and upgrades in SDN

In the realm of software-defined networking (SDN), ensuring robust maintenance operations and the consistent performance of switch operations, especially during maintenance and upgrades, is of paramount importance. Traditional SDN methods, both reactive and proactive, face challenges like extended convergence times, inefficient use of Ternary Content-Addressable Memory (TCAM) space, and unpredictable maintenance time. To tackle these issues and enhance maintenance operations, this paper introduces the Preventive Maintenance Routing Framework (PMRF) – a novel approach designed for uninterrupted upgrades in SDN settings. Our framework focuses on selecting reliable backup paths and timely isolation of the maintenance switch except critical switch, framed as an NP-hard mixed-integer linear programming problem. To address this complexity, we present a multi-objective heuristic algorithm that efficiently determines the best path for upcoming affected flows. Testing shows that, in varied network conditions, PMRF markedly reduced packet drops, potentially enhancing SDN operation efficiency, minimizing end-to-end delays, and maintaining failure recovery times below 50 ms and efficiently manage TCAM resources. In summary, PMRF offers a robust solution for optimizing network reliability and efficiency during maintenance operations and upgrades in core networks.

Ferroelectric Hafnia-Based M3D FeTFTs Annealed at Extremely Low Temperatures and TCAM Cells for Computing-in-Memory Applications.

In order to overcome the bottleneck between the central processor unit and memory as well as the issue of energy consumption, computing-in-memory (CIM) is becoming more popular as an alternative to the traditional von Neumann structure. However, as artificial intelligence advances, the networks require CIM devices to store billions of parameters in order to handle huge data traffic demands. Monolithic three-dimensional (M3D) stacked ferroelectric thin-film transistors (FeTFTs) are one of the promising techniques for realizing high-density CIM devices that can store billions of parameters. In particular, oxide channel-based FeTFTs are well suited for these applications due to low-temperature processes, nonvolatility, and 3D integration capability. Nevertheless, the M3D-integrated CIM devices including hafnia ferroelectric films need the high-temperature annealing process to crystallize the ferroelectric layer, making M3D integration difficult. When the FeTFTs are fabricated with an M3D structure, the high-temperature process causes thermal issues in the underlying devices. Here, we present the focused microwave annealed (FMA) oxide FeTFTs with M3D integration at a low temperature of 250 °C. We confirmed that the FeTFTs with metal-ferroelectric-metal-insulator-semiconductor structure exhibited a large memory window of 3.2 V, good endurance over 106 cycles, and a long retention time of 105 s. To understand the different electrical characteristics of FeTFTs in the top and bottom layers, we experimentally analyzed the density of the state of the oxide channel and ferroelectric properties of the ferroelectric gate insulator by using multifrequency capacitance-voltage measurement and nucleation-limited-switching model analysis, respectively. With our approach, we demonstrate for the first time a vertical stacked FeTFTs-based ternary-content-addressable memory (TCAM) cell for CIM application. We believe that the proposed M3D-stacked TCAM cells composed of FeTFTs can be used in high-density memory, energy-efficient memory, and CIM technology.

Packet Classification Using TCAM of Narrow Entries

Packet classification based on rules of packet header fields is the key technology for enabling software-defined networking (SDN). Ternary content addressable memory (TCAM) is a widely used hardware for packet classification; however, commercially available TCAM chips have only limited storage. As the number of supported header fields in SDN increases, the number of supported rules in a TCAM chip is reduced. In this work, we present a novel scheme to enable packet classification using TCAM with entries that are narrower than rules by storing the most representative field of a ruleset in TCAM. Due to the fact that not all rules can be distinguished using one field, our scheme employs a TCAM-based multimatch packet classification technique to ensure correctness. We further develop approaches to reduce redundant TCAM accesses for multimatch packet classification. Although our scheme requires additional TCAM accesses, it supports packet classification upon long rules with narrow TCAM entries, and drastically reduces the required TCAM storage. Our experimental results show that our scheme requires a moderate number of additional TCAM accesses and consumes much less storage compared to the basic TCAM-based packet classification. Thus, it can provide the required scalability for long rules required by potential applications of SDN.

FFRLI: Fast fault recovery scheme based on link importance for data plane in SDN

For many years, link fault recovery has always been a hotspot problem in Software-Defined Networking (SDN). Current researches mainly include proactive and reactive schemes. However, proactive scheme wastes the Ternary Content Addressable Memory (TCAM) and bandwidth resources seriously, and reactive scheme has a long recovery time. Hence, none of them qualifies as a complete solution. In this paper, we present a new two-stage fast fault recovery scheme based on link importance (FFRLI) to balance backup resource consumption and recovery time. In stage 1, FFRLI innovatively introduces Markov chains and pinning control to evaluate the importance and rank of different links, and labels them as main link, minor link and edge link. On this basis, in stage 2, we develop different recovery schemes and optimization objectives for different links. More specifically, for main links, we minimize the hops of backup path and install flow rules into switches in advance. Similarly, we store backup path of minor link in controller, and improve A-star algorithm to minimize hops and distance of backup path. Finally, FFRLI takes reactive recovery for edges link and adopts bidirectional Dijkstra to reduce backup path calculation time. Compared to existing state-of-the-art solutions, the simulation results present that FFRLI can effectively balance the consumption of backup resource and fault recovery time, and achieve fast fault link recovery.

Investigation on floating-gate field-effect transistor for logic-in-memory application

In this paper, we present analysis results on the applicability of a previously introduced memory device, floating-gate field-effect transistor (FGFET), to a logic-in-memory (LiM) system for the first time. Device optimization and compact modeling were performed using a well-calibrated technology computer-aided design model and the results of applying LiM circuits were arranged. Device optimization in the 32 nm technology node was conducted by assessing the device performance in terms of memory window, retention time, and write speed. After device optimization, the operational characteristics were analyzed by applying the proposed compact model to a full adder (FA) circuit and a ternary content addressable memory (TCAM) circuit with LiM characteristics. Compared to FA and TCAM circuits composed of conventional FETs, the FGFET-based circuits demonstrated superior performance in terms of area and operating characteristics, implying that they offer significant potential for applications in silicon-based LiM technology.

A novel algorithmic Data-Collision SDRAM-based TCAM architecture on FPGA

Ternary Content-Addressable Memory (TCAM) is one of the most effective methods for high-speed data searching in networking infrastructure. Despite the excellent performance and large look-up table, application-specific integrated- circuit-based TCAMs cost massive power supply and are challenging to configure. Field-Programmable Gate Arrays (FPGAs) have become the alternative solution for integrating TCAM due to their minimal power consumption and reconfigurability. Methods using on-chip registers, BRAMs, or LUTRAMs to implement large-size TCAM suffer excessive resource consumption. Researchers introduced DDR-SDRAM-based CAM to provide high-performance and economic packet inspections to overcome such issues; however, they only support binary look-up. This paper presents a novel algorithmic Data-Collision TCAM architecture on FPGA for SDRAM compatibility. The proposed SDRAM- based TCAM supports ternary value look-up function for practical Ethernet packet processing. The architecture outperforms conventional TCAMs regarding BRAMs, logics consumption, and look-up table sizes. The proposed architecture is the first SDRAM-based TCAM on FPGA with a 128Mbyte look-up table.

FTODefender: An efficient flow table overflow attacks defending system in SDN

Software-Defined Networking (SDN) is a promising architecture that disentangles the control plane from the data plane. A mainstream southbound protocol for controller-to-switch communication in SDN is OpenFlow. In an OpenFlow-enabled network, SDN switches are connected to the logically centralized control plane, which issues control messages to direct packet forwarding and processing in the data plane. Given that the finite capacity of physical flow tables of switches, typically implemented with ternary content addressable memory (TCAM), attackers have the ability to carry out Denial-of-Service (DoS) attacks aimed at depleting the TCAM’s resources and causing an overflow of the flow table. In this paper, we propose FTODefender, a method combining eviction and cut-off attack sources to detect Low-rate Flow Table Overflow (LFTO) attacks and mitigate this kind of attacks in time. FTODefender consists of two modules: Detector and Mitigator. Detector periodically examines the flow table and extract four specific detection features. It then employs the trained CRITIC weights to calculate the detection score based on these extracted features to verify if the LFTO attack has happened. Mitigator computes the features for each flow and utilizes the LightGBM-LR classification model to identify attack flows among all flows. Then, the module evicts the malicious rules to mitigate attacks. Finally, Mitigator counts the occurrence of each source IP address in the eviction list, determines the attacker IP based on a predefined threshold, and issues a flow rule to drop all packets originating from the attacker’s IPs to sever the attack sources. Simulations show the effectiveness of FTODefender in mitigating the LFTO attacks, which proves that FTODefender is a practical solution to flow table overflow attacks.

Dynamic Power Reduction in TCAM Using Advanced Selective Pre-Charging of Match Lines

In this paper, we propose a power-efficient memory operation, selective match line precharge, based on an analysis of power consumption in ternary content-addressable memory (TCAM). A statistical study reveals that, on average, 58% of power dissipation related to the match line operation is saved by deactivating the unnecessary swing of match lines. The improvement has been simulated and proved using 180 nm CMOS technology.