Ternary Bit Research Articles

A Novel Physical Unclonable Function Based on Silver Nanowire Networks

AbstractAs digital security demands continue to rise, physical unclonable functions (PUFs) have emerged as a potential solution for providing unique identifiers and cryptographic keys. However, conventional memory‐based PUFs have limited encoding capacity, which can compromise their security. Herein, an Ag nanowire‐based PUF that offers a high encoding capacity is introduced. The prototype PUF leverages the intrinsic topology of the nanowire network for encoding, which enables to achieve encoding capacities that are on the order of nn−2. The encoding method for a 4‐node PUF is validated and its encoding capacity distribution at binary and ternary bit levels is assessed. The ternary bit encoding method allows for more detailed differentiation of the internal topological connection structure of the PUF, resulting in a larger encoding capacity. Additionally, an authentication system that is proposed. For a 7 × 7 array PUF, the estimated decryption time is ≈1.5*1058 years, demonstrating the PUF's resistance to attacks. The Ag nanowire‐based PUF design offers a promising approach to enhancing authentication system security and overcoming limitations of existing PUFs. Further exploration of this innovative PUF technology in the realm of hardware security can have significant implications for digital security in modern devices.

Twin physically unclonable functions based on aligned carbon nanotube arrays

Physically unclonable functions (PUFs) are a promising technology for generating cryptographic primitives using random imperfections in a physical entity. However, the keys inside PUFs are still vulnerable as they must be written into non-volatile memories and shared with participants that do not hold the PUF before secure communication. Here we show that pairs of identical PUFs (twin PUFs) can be fabricated together on an aligned carbon nanotube array and used for secure communication without key pre-extraction and storage. Two rows of field-effect transistors are fabricated perpendicular to the carbon nanotube growth direction, randomly producing three types of transistor channel—based on metallic nanotubes, semiconducting nanotubes and no nanotubes—that can be used to extract ternary bits for use as a shared key. The twin PUFs exhibit high uniformity, uniqueness, randomness and reliability, as well as a consistency of approximately 95%. We show that separated twin PUFs can provide secure communication with a bit error rate of one bit per trillion via a fault-tolerant design.

An Efficient Ultra-Low-Power and Superior Performance Design of Ternary Half Adder Using CNFET and Gate-Overlap TFET Devices

This paper presents a novel ultra-low power yet high-performance device and circuit design paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs (GOTFETs) and Carbon Nanotube FETs (CNFETs). One of the distinguishing novelty reported in this work is the introduction of an innovative GOTFET device, which exhibits more than double the on-currents I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> and less than 1/10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> the off-currents I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> of equivalent, equally-sized mosfets at the same technology node. Most of the ternary logic designs reported earlier in the literature encode ternary bits into binary for combinational functionality and then use an Encoder to get back ternary output. Unlike the earlier designs, this paper presents a novel and significantly more efficient approach of directly designing ternary logical functions with Low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> Transistors (LVT) and High V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> Transistors (HVT) using CNFET and GOTFET technologies. The new approach simplifies the design and reduces the required transistor count & interconnects, thereby reducing the delays and power consumption. The proposed Ternary Half Adder (THA) circuit, designed using CMOS, enables a 52% reduction in transistor count compared to the conventional CMOS designs available in the literature. The THA implemented with CNFET exhibits 27 ps (87% lower delay than similar CMOS design and consumes 2.4 μW power (11% lower than CMOS). On the other hand, CGOT THA exhibits 101 ps (51% lower delay than similar CMOS design) and consumes merely 1.26 μW power (53% lower than CMOS, in ultra-low power regime). The overall decrease in the Power Delay Products (PDPs) are 88% and 77%, respectively, in the proposed CNFET and CGOT THA circuits compared to the CMOS THA.

Phase tristability in parametric three-photon down-conversion.

This Letter shows that the parametric processes of spontaneous three-photon down-conversion is accompanied by phase tristability of the sub-harmonic signal. The oscillations of the signal in a resonant cavity are modeled through an analytically solvable second-order nonlinear oscillator. Self-sustained oscillations of the signal at a finite amplitude are found to be equally probable in three states with uniform phase contrasts. The onset of oscillations is a case of bifurcation from infinity. The stability of the ternary states is proven through an energy landscape function that identifies the attractor basins of the three states. An analogy is drawn between the oscillation threshold of a three-photon down-conversion oscillator and a first-order phase transition. The investigated phase-tristable oscillator can serve as a classical ternary bit for unconventional computing applications.

Ternary representation of N (N = 1 or 2)-input and 1-output algorithmic self-assembly demonstrated by DNA

Deoxyribonucleic acid (DNA) is effective for molecular computation because of its high energy efficiency, high information density, and parallel-computing capability. Although logic implementation using DNA molecules is well established in binary systems (base value of 2) via decoration of hairpin structures on DNA duplexes, systems with base values of >2 (e.g. 3, corresponding to a ternary system) are rarely discussed owing to the complexity of the design and the experimental difficulties with DNA. In this study, DNA rule tiles that participate to form algorithmic DNA crystals exhibiting the ternary representation of an N (N = 1 or 2)-input and 1-output algorithmic assembly are conceived. The number of possible algorithmic patterns is in the ternary N-input and 1-output logic gate. Thus, the number of possible rules is 27 (=33) for a 1-input and 1-output algorithmic logic gate and 19 638 (=39) for a 2-input and 1-output algorithmic logic gate. Ternary bit information (i.e. 0-, 1-, and 2-bit) is encoded on rule tiles without hairpins and with short and long hairpins. We construct converged, line-like, alternating, and commutative patterns by implementing specific rules (TR00, TR05, TR07, and TR15, respectively) for the 1-input and 1-output gate and an ascending line-like pattern (with the rule of TR3785) for the 2-input and 1-output gate. Specific patterns generated on ternary-representing rule-embedded algorithmic DNA crystals are visualized via atomic force microscopy, and the errors during the growth of the crystals are analyzed (average error rates obtained for all experimental data are <4%). Our method can easily be extended to a system having base values of >3.

Neuron inspired data encoding memristive multi-level memory cell

Mapping neuro-inspired algorithms to sensor backplanes of on-chip hardware require shifting the signal processing from digital to the analog domain, demanding memory technologies beyond conventional CMOS binary storage units. Using memristors for building analog data storage is one of the promising approaches amongst emerging non-volatile memory technologies. Recently, a memristive multi-level memory cell for storing discrete analog values has been developed in which memory system is implemented combining memristors in voltage divider configuration. In given example, the memory cell of 3 sub-cells with a memristor in each was programmed to store ternary bits which overall achieved 10 and 27 discrete voltage levels. However, for further use of proposed memory cell in analog signal processing circuits data encoder is required to generate control voltages for programming memristors to store discrete analog values. In this paper, we present the design and performance analysis of data encoder that generates write pattern signals for 10 level memristive memory.

Nonvolatile organic field-effect transistors memory devices using supramolecular block copolymer/functional small molecule nanocomposite electret.

Organic field-effect transistors (OFETs) memory devices based on hybrid nanocomposite electret were fabricated by cooperative supramolecular polystyrene-block-poly(4-vinylpyridine) (PS-b-P4VP) with two different block compositions (asymmetric L1 and symmetric L2) that contain hydroxyl-functionalized ferrocene small molecules (FMs). Because of the selective hydrogen interaction between the hydroxyl groups of FM and pyridine groups in P4VP block, the small FMs can preferentially disperse in the P4VP nanodomain, which can be used as nanostructured charge-trapping nanocomposite electret (L1-FMX and L2-FMX) under solvent-annealing process. The charge-storage functionalities can be easily tailored by morphologies of the hybrid nanocomposite thin film and spatial distribution of the FM molecules in which the relative molecular mass of block copolymers and the FM loading ratio can further control both of them. These block copolymer nanocomposite thin film electrets with charge-controlling guest FM for OFETs memory devices exhibit significant features including the ternary bits storage, high-density trapping sites, charge-carrier trapping of both polarities (ambipolar trapping), and solution processing that can make important progress for future advanced storage and memory technology.

Ferroelectric and magnetic properties of CdMnS films prepared by coevaporation

We report on impurity ferroelectricity and ferromagnetic properties in semiconductor-structured CdMnS films. We observed ferroelectric hysteresis in CdMnS. A remnant polarization of 1.72 μC/cm2 and a coercive field of 14.3 kV/cm were obtained in samples with Mn concentration below 2%. The coevaporated CdMnS samples become ferromagnetic when doped with Au, with a spontaneous magnetization of 1.39×10−6 emu and a coercive magnetic field of 75.4 gauss at 10 K, and the Curie point was found to be higher than room temperature. Through magnetic force microscopy, we observed clear magnetic clusters with sizes ranging from a few nanometers to 102 nm, and found the magnetization to be highly dependent on Au concentration. A combination of this ferroelectricity in CdMnS and ferromagnetism in Au-doped CdMnS may find use in ternary bit nonvolatile memory devices.