Terms Of DC Research Articles

Design of experiments for fitting regression models on the tubular SOFC [formula omitted]: Screening test, response surface analysis and optimization

The SOFC CHP 100 kW e Field Unit built by Siemens is operating at the Gas Turbine Technologies in Torino. The generator started up on June 2005, and is delivering around 100 kW e of AC electrical energy to the grid and 55 kW t of thermal energy, providing heating and cooling for the facility's buildings. An experimental plan has been designed by applying the factorial analysis. Before performing the experiments on the plant, this approach has been applied to a computer model simulation: a 2 3 factorial analysis has been applied to the generator model (independent variables: fuel utilization factor, air utilization factor and air temperature at the generator inlet). First-order regression models are obtained for the investigated dependent variables (i.e. DC power, recovered heat, combustion zone temperature, etc.). The data are analyzed by applying the response surface methodology. Finally, constrained optimization methods are applied to investigate optimal operation points in terms of DC generated power or exhausts’ recovered heat. A comparison with the actual operation point of the SOFC generator is shown.

Device performance improvement of InGaP/InGaAs doped-channel FETs

Partial drain/source ohmic recess InGaP/InGaAs/GaAs doped-channel field-effect transistors (OR-DCFETs) are proposed and fabricated in this study. The proposed ohmic recess process reduces the parasitic ohmic alloyed resistance caused by the undoped Schottky layer and therefore improves the device performance in terms of dc and source resistance, as well as RF characteristics. We compare the proposed devices with the DCFETs using the conventional process by means of experiments, where the Yang-Long method is used to analyze the effect of parasitic source resistances.

2D device-level simulation study of strained-Si pnp heterojunction bipolar transistors on virtual substrates

A novel strained-Si pnp heterojunction bipolar transistor (HBT) design, suitable for virtual substrate technology, is proposed that is inherently free from the detrimental valence band barrier effects usually encountered in conventional SiGe pnp HBTs on silicon. It takes advantage of the heterojunction formed between a strained-Si layer and a relaxed SiGe buffer (virtual substrate), whose associated valence band offset appears favorable for minority hole transport at the base/collector junction. From two-dimensional (2D) numerical simulation, it is found that the newly proposed strained-Si pnp HBT substantially outperforms the equivalent BJT on a silicon substrate in terms of DC and high-frequency characteristics. A threefold increase in maximum current gain β, a fourfold improvement in peak f t and a 2.5 times increase in peak f max are predicted for strained-Si pnp HBTs on a 50% Ge virtual substrate in comparison with identical conventional silicon pnp BJTs.

Ga0.51In0.49P/InxGa1−xAs/GaAs doped‐channel FETs (DCFETs) and their applications on monolithic microwave integrated circuits (MMICs)

AbstractIn this paper, lattice‐matched Ga0.51In0.49P/GaAs and strained Ga0.51In0.49P/In0.2Ga0.8As doped‐channel FETs (DCFETs) were investigated in terms of DC and microwave performances, including frequency response, noise figure, power‐added efficiency (PAE), and output power. In addition, small‐signal and large‐signal models were created for designing monolithic microwave integrated circuits (MMICs). The heterostructures were both grown by gas‐source molecular beam epitaxy (GSMBE) on semi‐insulating (100) GaAs substrates. In situ reflection high‐energy electron diffraction (RHEED) was used to calibrate the growth rate of InP and GaP. Because of the high etching selectivity between Ga0.51In0.49P and In0.2Ga0.8As/GaAs, the uniformity of the measured electrical properties of our fabricated devices is quite satisfying, which indicates that these Ga0.51In0.49P/InxGa1−xAs structures are very suitable for mass production. © 2003 Wiley Periodicals, Inc. Microwave Opt Technol Lett 39: 56–62, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.11126

Microwave power performance comparison between single and dual doped-channel design in AlGaAs/InGaAs HFETs

Single and dual doped-channel AlGaAs/InGaAs FETs (DCFETs) were fabricated, characterized, and compared with each other in terms of dc, rf, and power performance. The dual doped channel design provides a higher current density, and a better linear operation range over a wide gate bias range and frequency. A 1 μm-long gate dual-DCFET operated at 1.9 GHz demonstrates a power-added efficiency of 51.5%, a gain of 19 dB, and an output power density of 305 mW/mm at 2.5 V. This performance suggests that dual doped-channel design is more suitable for linear and high power microwave device applications.

High-performance Ga/sub 0.51/In/sub 0.49/P/GaAs airbridge gate MISFET's grown by gas-source MBE

Ga/sub 0.51/In/sub 0.49/P/GaAs MISFET's, in which Ga/sub 0.51/In/sub 0.49/P insulating layer was inserted between the gate metal and the channel layer, were compared with MESFET's experimentally and theoretically in terms of DC and microwave performance. Devices performance were evaluated by varying the thickness of the insulating layer. Wide and flat characteristics of g/sub m/, g/sub t/, and f/sub max/ versus drain current (or gate voltage) together with a high maximum current density (above 610 mA/mm) were achieved for devices with insulating layer thickness of 50 mn and 100 mm. Moreover, the maximum values of J/sub t/'s and f/sub max/'s for a 1-/spl mu/m gate length device both occurred when t was between 50 and 100 mn. We also observed that parasitic capacitances and gate leakage currents were minimized by using the airbridge gate structure, and thus high-frequency and breakdown characteristics were greatly improved, These results demonstrate that Ga/sub 0.51/In/sub 0.49/P/GaAs airbridge gate MISFET's with insulating layer thickness between 50 and 100 mn were very suitable for microwave high-power device applications.

Prediction of frequency effect in high temperature fatigue crack growth using damage factors

An earlier modification of the Paris law for the growth of deep cracks in the linear elastic fracture mechanics regime is extended to include a term enabling the prediction of cyclic crack growth rates at low frequencies. The relation requires (i) a reference growth law under continuous cycling at the appropriate elevated temperature and (ii) a specified, dimensionless degradation term, defined as Dc, the creep/oxidation damage per cycle, which increases as the applied frequency decreases or as the dwell time at peak load is prolonged. The relationship is validated against data from the previous analysis on low alloy ferritic and austenitic steels in the range 538–650°C and against further published results on Ni-based alloys at temperatures up to 700°C. It appears that for the former series oxidation is the dominant damaging mode, whereas a linear creep damaging mechanism is manifest in the Ni-based alloys. Moreover, levels of cyclic damage in terms of Dc are higher in the latter, ranging between 10−3 and 5 × 10−1 compared with 10−4 to 5 × 10−2 for the steels. A brief comparison is made with damage factors arising from the high strain fatigue deformation mode at elevated temperatures and other models for the prediction of frequency effects are discussed.

The stretched quadrupole ion trap: Implications for the Mathieu au and qu parameters and experimental mapping of the stability diagram

AbstractThe effect of the radial and axial dimensions on the Mathieu stability diagram (in terms of DC and RF voltages) is discussed with relation to the ‘stretched’ geometry employed in the Finningan MAT quardrupole ion‐trap mass spectrometer (ITMS). Equations are presented for the conversion of the Mathieu au and qu parameters to DC voltages and RF voltages, respectively, and vice versa on the ITMS. A TURBOBASIC program is discussed which will provide data for graphing of a stability diagram in (RF, DC) space. Experimentally determined boundaries of the stability diagram are in good agreement with an approximate model for the stretched trap.

Hot-carrier-induced degradation in reoxidized-nitrided-oxide n-MOSFETs under mixed AC-DC stressing

Reduced degradation rate can be observed for reoxidized-nitrided-oxide (RNO) n-MOSFETs under dynamic stressing versus the corresponding static stressing. A new degradation mechanism is proposed in which trapped holes in gate oxide are neutralized by the hot-electron injection, with no significant generation of interface states because of the hardening on the Si-SiO/sub 2/ interface by nitridation/reoxidation steps. The RNO device degradation during AC stressing arises mainly from the charge trapping in the gate oxide rather than the generation of interface states. Moreover, the AC-stressed RNO devices are significantly inferior to the fresh RNO devices in terms of DC stressing, possibly due to lots of neutral electron traps in the gate oxide resulting from the AC stressing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A cohesive zone model for dynamic shear faulting based on experimentally inferred constitutive relation and strong motion source parameters

To understand constitutive behavior near the rupture front during an earthquake source shear failure along a preexisting fault in terms of physics, local breakdown processes near the propagating tip of the slipping zone under mode II crack growth condition have been investigated experimentally and theoretically. A physically reasonable constitutive relation between cohesive stress τ and slip displacement D, τ = (τi − τd)[1 + α log (1 + βD)] exp (−ηD) + τd, is put forward to describe dynamic breakdown processes during earthquake source failure in quantitative terms. In the above equation, τi is the initial shear stress on the verge of slip, τd is the dynamic friction stress, and α, β, and η are constants. This relation is based on the constitutive features during slip failure instabilities revealed in the careful laboratory experiments. These experiments show that the shear stress first increases with ongoing slip during the dynamic breakdown process, the peak stress is attained at a very (usually negligibly) small but nonzero value of the slip displacement, and then the slip‐weakening instability proceeds. The model leads to bounded slip acceleration and stresses at and near the dynamically propagating tip of the slipping zone along the fault in an elastic continuum. The dynamic behavior near the propagating tip of the slipping zone calculated from the theoretical model agrees with those observed during slip failure along the preexisting fault much larger than the cohesive zone. The model predicts that the maximum slip acceleration be related to the maximum slip velocity and the critical displacement Dc by , where k is a numerical parameter, taking a value ranging from 4.9 to 7.2 according to a value of τi/τp (τp being the peak shear stress) in the present model. The model further predicts that be expressed in terms of and the cut off frequency fmaxs of the power spectral density of the slip acceleration on the fault plane as and that in terms of Dc and fmaxs as . These theoretical relations agree well with the experimental observations and can explain interrelations between strong motion source parameters for earthquakes. The pulse width of slip acceleration on the fault plane is directly proportional to the time Tc required for the crack tip to break down, and fmaxs is inversely proportional to Tc.