Chip Temperature Distribution Research Articles

New discoveries of stress fluctuations at the tool-chip interface and sticking tool tendency in metal cutting processes

Addressing the issue of sticking tools during the metal cutting process is crucial for enhancing cutting efficiency and ensuring industrial safety. This study employs molecular dynamics (MD) simulations to investigate single-crystal SiC tools and 27 different grain orientations of single-crystal pure metal workpieces (Ni, Cu, Co, and Fe). MD models were established to simulate the nanocutting and tool retraction processes. This study revealed a new phenomenon of stress fluctuations at tool-chip interfaces and proposed a new theory on the relationship between stress fluctuations and metal sticking tool tendencies. Research indicates that during nanocutting, the normal stress distribution at the tool-chip interface of different materials exhibits the same periodic fluctuation (T=0.5a, where a is the tool lattice constant). The greater the stress fluctuation is, the greater the sticking tool tendency. By fitting the results for 27 workpieces, an approximate relationship was established. For metals with the same lattice type, such as FCC-structured Ni and Cu, the stress fluctuation and sticking tool tendency are both greater when the cutting orientation is 11111¯0, and the chip morphology and temperature distribution are similar. Through the analysis of lattice transformation, atomic shear strain, and temperature field, this study explored the microscopic mechanisms and thermomechanical theories underlying the new findings of stress fluctuations and sticking tool tendencies. The stress fluctuation distribution at the tool-chip interface is a new discovery that differentiates nanocutting from traditional processing models. Future research can further investigate the cutting behavior of complex materials under complex conditions, which will help to further elucidate the mechanism of sticking tools during processing.

Predictive Placement of IC Chips using ANN-GA Approach for Efficient Thermal Cooling

In this research, numerical modelling is used to explore the heat transfer through natural convection capabilities of nine aluminum integrated circuit chips that are installed on substrate board. The goal is to figure out where on the substrate board these IC chips would be best placed if they were arranged differently. The dimensionless parameter (λ) plays a very essential role, and by applying a hybrid technique consisting of ANN and GA. ANSYS Icepack calculates IC chip temperature distributions in 3D steady state numerical simulations. It has been shown that the form, dimensions, and IC chips' substrate board positioning affects their operating temperature. In comparison to the strategies that have been used in the past, hybrid optimization is the strategy that has shown to be the most reliable in properly predicting how the IC chips would be arranged on the substrate board. It has been observed that higher values of one of these parameters lead to a reduction in the maximum temperature surplus. A correlation has been established to illustrate this relationship as it increases. The most favorable simulation outcomes are utilized to drive a genetic algorithm (GA), which identifies the optimal configuration ensuring that the temperatures of the heat sources remain well below their specified maximum operating conditions, as outlined in the data sheets. The maximum temperature variation between the lowest and highest extreme configurations ranges between 4 - 8%. The smallest size IC chip, U2 with high heat dissipation rate attains the maximum temperature in the configuration, however, the temperature variation for the low powered IC chips U3, U4 and U7 are very small. Found good agreement of both the data with an error band of 10%, and thus confirms the accuracy of the network.

Simulation and experimental study on the effect of deformation on heat and mass transfer in potato chips during superheated steam drying

AbstractSuperheated steam drying is a drying technology with enormous potential and numerous advantages. Volume change and substantial deformation will occur on the materials to be dried during the superheated steam drying, which would affect the heat and mass transfer of the sample. However, the influence mechanism is not clear. Therefore, the nonuniform volume change of potato slices was studied, and the deformation model (DM) and the non‐DM (NDM) were constructed and verified to study the heat and mass transfer processes of the sample. The results showed that there was little difference between the measured and simulated temperatures based on DM and NDM with a maximum error of 4.22% and 5.03%, respectively, but there was obvious difference between simulated moisture contents with a maximum error of 5.76% and 12.21%, respectively. The volume in DM was in good agreement with the experimental data. Temperature distribution and moisture distribution in potato chips during superheated steam drying were nonuniform and the maximum temperature gradient and moisture gradient appeared in the early period. The moisture gradient existed in the whole drying process, and the stress caused by the moisture gradient was the main factor causing the drying deformation.Practical applicationsThis work can reveal that the volume change and substantial deformation have a significant impact on the heat and mass transfer during drying. In production practice, there are many similar phenomena. The results would be helpful to understand the heat and mass transfer mechanism, optimize quality parameters to obtain better products in potato drying industry, and expand the applied range of the superheated steam drying technology.

Transient temperature distribution in a multilayer semiconductor device with dynamic thermal load and non-uniform thermal contact resistance between layers

The thermal management challenge in microelectronic chips is exacerbated by their multilayer architecture and manufacturing processes that introduce non-uniform thermal contact resistance between adjacent layers. Most of the past work on development of thermal models to predict temperature distribution in microelectronic chips either does not account for such thermal contact resistance at all, or simply assumes it to be spatially uniform. This work presents an exact analytical solution for the transient temperature distribution in a multilayer chip with non-uniform thermal contact resistance between layers as well as dynamic, non-uniform heat generation. The problem is solved by first carrying out a Laplace transformation and then implementing a series solution, the coefficients of which are determined by solving a set of algebraic equations derived from the non-uniform thermal contact resistances between adjacent layers. While the problem is solved for a general M-layered chip, the solution for the practical case of a two-layer chip is also provided. Results indicate that the temperature distribution and its evolution over time is determined by the nature of the non-linear thermal contact resistance, and its overlap with the dynamic heat loads imposed on the chip. The impact of these and other relevant parameters is examined in detail. Results presented here improve the fundamental understanding of thermal transport modeling in multilayer semiconductor chips, with possible applications in other multilayer engineering systems as well.

Coupled Electrical–Thermal–Fluidic Multi-Physics Analysis of Through Silicon Via Pin Fin Microchannel in the Three-Dimensional Integrated Circuit

Abstract To solve the thermal management problem in the three-dimensional integrated circuit (3D-IC) with high integration and multilayer, this paper establishes a 3D-IC interlayer microchannel model with various embedded TSV micropin fins to explore the temperature distribution of chips and the flow velocity distribution inside the microchannel. The paper selects the sense amplifier and the half adder as the heat source of the memory and processor in the calculation model. The power densities of the sense amplifier and the half adder are 885 kW/m2 and 1.832 MW/m2 combined with the layout size, respectively. Meanwhile, the effects of the shape and arrangement of TSV micropin fins on the flow and heat transfer characteristics are investigated. The result shows that the 1.2:1 diamond micropin fin microchannel with staggered arrangement has the best overall flow and heat transfer performance. Compared with the basic circular micropin fin with the in-line arrangement, the average Nusselt number of this microchannel is improved by 3.20–3.37 times, and the maximum temperature of chips is controlled at 325.92–312.43 K for Re = 628–1819.

(Invited) 3DIC Hierarchical Thermal and Mechanical Analysis with Continuum and Atomistic Modeling

3D IC heterogeneous integration technologies employ numerous materials with widely varying thermal and mechanical properties and distinct deformation behaviors. During 3D integration processes, the constituent materials undergo various thermal cycles. Because of thermal expansion coefficient mismatch, the materials are essentially subject to mechanical loadings for these thermal ramps. The resulting chip, package, and board interactions lead to 3D stack warpage, silicon mobility variation, and material damage. Under operation conditions, heat can be trapped between insulation layers and leads to nonuniform temperature rises. Elevated local temperatures can change carrier mobility, relax mechanical stress, and affect material deformation behaviors. Consequently, these local temperature rises can affect device performance, structure integrity, and material reliability. To accurately assess these thermal and mechanical effects, extract design rules, optimize designs, and develop performance and reliability mitigation methodologies, it is of paramount importance to characterize material deformation and interface de-bonding behaviors, map chip temperature distributions, and analyze stress hotspot evolutions during integration process and under operation conditions while developing 3D IC integration technologies [1].In this study, a multiscale hierarchical modeling approach is assembled to analyze thermal, mechanical, and material deformation and interface de-bonding behaviors under 3D integration process and operation conditions for a newly designed 3D IC package with a 2nm SOC die copper-bonded on an RDL interposer [2]. The 3DIC structures are constructed directly using GDSII design and ITF technology data [3]. Each structural layer is divided into small smear tiles. Each tile is represented by anisotropic thermal and mechanical properties that depend on local feature patterns in the tile. Under given operation conditions, power grids are generated and used as heat sources for thermal analysis. For multiscale hierarchical modeling, the global thermal and mechanical analyses that call for coarse grain resolution are first performed. The subsequent local analyses that provide fine grain resolution in areas of interests utilize boundary conditions that are extracted from the global analyses. The material deformation and interface de-bonding behaviors are simulated using molecular dynamics [4]. Several 3D integration design options are explored. The 3D configuration effects on chip temperature distributions during operations, stack warpages, silicon mobility variations, and chip package interaction induced stress hotspots are examined. The elevated temperature impacts on material deformation and de-bonding process are also investigated.

Experimental Study and Finite Element Analysis of Temperature Reduction and Distribution During Machining of Al-Si-Mg Composite Using Deform 3D

Composite materials are promising materials in the manufacturing industry due to the quality of their materials. However, in transforming these materials, the machining process experiences a high-heat generation rate, which has led to the study of temperature distribution, and reduction analysis at the cutting region. High-temperature generation during machining operation leads to thermal deformation on the developed component or parts, affecting the operation life span of the component. Thus, this study investigated the effect of mineral oil-based-Multi-walled carbon nanofluid (MWCNTs) compared to pure mineral oil in the turning of aluminum-silicon magnesium metal composite (AlSiMg) on temperature reduction and distribution. The nanofluid was prepared with 0.4g of MWCNT to 1 liter of mineral oil. The study employed the energy dispersive spectrometer to obtain the chemical composition of the developed nanofluid. Furthermore, Finite element software DEFORM 3D v11.0 uses a lagrangian incremental approach to simulate chip formation and temperature distribution on the workpiece. Also, to study the effects of the machining parameters on the temperature distribution. The experiment results showed a significant reduction of 11.9% in temperature when machining with nanofluid compared to pure mineral oil. The simulation results showed that the temperature increases as the cutting speed and feed rate increase. The minimum temperature via the DEFORM 3D Finite Element Model simulation was achieved at spindle speed 870 rpm, feed rate 2 mm/rev, and depth-of-cut 1 mm. In conclusion, the study recommends that the manufacturing industry employ the optimized machining parameters during the turning of AlSiMg metal matrix composite for a sustainable machining process.

Ratio Study of High-Pressure Lubrication and Cutting Parameters Effects on Machining Operations and Its Effect Towards Sustainable Machining: A Review

Machining is the art of developing sustainable mechanical components by transforming solid raw materials into the finished product. Because for any Nation to achieve sustainable development, the Nation must have quality manufacturing industries. This paper summarizes existing articles on the effects of high-pressure lubrication conditions on chip formation and temperature distribution. Also, surface roughness, tool wear, and vibrations in machining operations when considering the current trend. Furthermore, the study of nano-lubricant and their application in reducing friction and temperature were also reviewed. The study also examined other lubrication conditions, cutting parameters with the high-pressure machining operations to draw a definite conclusion. The review confirms that applying a high-pressure lubrication system is very efficient. However, it has some challenges. Cooling technology is not built into the system, discovered during this review. Therefore, the study will recommend a developed machine that can function in multiple faces. Industrial 4.0 additive manufacturing techniques can build the cryogenic system—making the lubricant delivery machine a sustainable technology in machining operation. A high-pressure-cryogenic-MQL lubrication process is needed for sustainable machining operations of various alloys and metal composite materials for automobile, aerospace, and structural applications. The sustainable lubrication system will also help eradicate high-temperature occurrence in the machining region with a sustainable way of removing the chips without experiencing chip breakage at the cutting region.

Temperature Distribution Evaluation of Single Chip by Multiple Currents V CE (T) Method

With the ever-growing power density in power electronics, the temperature difference between the center and the edge of a chip can easily exceed 40 K, which poses a serious challenge to the reliability of power devices, and evaluation of single-chip temperature distribution will be more significant than classical virtual junction temperature for reliability assessment. In this article, a multicurrent V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> ( T) method is proposed to evaluate the single-chip temperature distribution. Unlike the conventional V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> ( T) method measuring the saturation voltage at only one small measurement current, this method requires that the voltages are measured at multiple different measurement currents, and then, the temperature distribution is obtained by solving a system of nonlinear equations. To improve the accuracy of the solution, the chip temperature distribution is represented by a mathematical function, which can greatly reduce the unknown parameters in the equations. Two common different shapes (square and rectangle) of the chip are chosen as research objects, this method is successfully applied in the dc power cycling test and verified by the infrared (IR) camera, and the calculation results agreed well with experimental results. Moreover, the possible effects of the introduction of mathematical models on the evaluation results have been discussed. The proposed method extends the conventional V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> ( T) method and finds its capability in chip temperature distribution evaluation, which could help investigate fatigue failure from different perspectives.

Water loss and partitioning of the oil fraction of mushroom chips using ultrasound-assisted vacuum frying

Sonication and microwave treatments for vacuum frying (VF) were studied to achieve the optimal frying conditions and improve the quality of fried products. Button mushrooms were used as a raw material. VF, microwave-assisted vacuum frying (MVF), ultrasound-assisted vacuum frying (UVF), and microwave combined with ultrasound VF (UMVF) techniques were used to produce the mushroom chips. Moisture content, oil partitioning coefficient (Kp), dielectric properties (DP), water activity (aw), and temperature distribution of chips were measured and compared among different frying methods. The UMVF increased the moisture evaporation rate and reduced the oil content of chips compared to other treatments. The Kp of UMVF was 0.069, whereas, for UVF, MVF, and VF, it was 0.041, 0.050, and 0.034, respectively, indicating that sonication could reduce oil penetration into the product. Odor profile analysis using an e-nose suggested that the sonicated chips had the most acceptable flavor parameters. The treatments did not significantly affect the aw, which ranged from 0.58-0.37. Whereas, the DP were enhanced. The UMVF process was shown to be a viable technology that could be used for frying to obtain high-quality products.

The Influence of Solder Void on IGBT Temperature

The void in solder layer is the main factor that causes bad heat dissipation of IGBT (Insulated Gate Bipolar Transistor) module. Based on the seven-layer structure of IGBT, this article established a three-dimensional finite element model of IGBT module packaging structure and carried out its thermal analysis, then had a study on the effect of welding layer void on the temperature of IGBT chip. The overall distribution of IGBT module with or without solder hole is compared, meanwhile the article analyzed the effects of void type, size, shape, number and distribution on the temperature distribution of IGBT chips. The results show that the void in the solder layer of the chip has a great influence on the temperature of the chip. The influence of penetrating voids on chip temperature is greater than that of non-penetrating voids, the bigger the single hole is, the higher the temperature of IGBT chip. Voids of the same shape have greater influence on chip temperature at edge and corner positions than those inside the welding layer. The more concentrated the distribution of multiple holes, the higher the chip’s temperature. Therefore, in order to improve the reliability of IGBT, it is necessary to avoid voids in the chip welding layer during the packaging process.

Analytical model of cutting temperature field in workpiece including uncut chip layer

To understand the nature of chip formation in cutting, the study of temperature field in the uncut chip layer of the workpiece is extremely important. In this study, the temperature field for the uncut chip layer is modeled using the heat source projection at different depths of the layer along the cutting speed direction to obtain the different heating times of points at corresponding depths. It is based on the model of the cutting temperature field in the machined surface layer of the workpiece, as proposed in the previous paper of the authors. The temperature distribution in both uncut chip and machined surface layers are thus achieved, and the temperature penetration depths in the machined surface layer are compared with experiment results. The results show that the computed isotherms on the boundary of the uncut chip and machined surface layers are continuous and smooth, indicating that the temperature field model for the uncut chip layer is correct. The temperature field for the nonplanar primary shear plane heat source is also modeled by introducing the curve integral. This is considerably significant in the conduct of further research on the temperature field in micromachining considering size effects and in machining using restricted contact tools, such as groove-type chip breaker tool, double-rake-angled tool, rounded-edge tool, and tool with built-up edge.

Improved IGBT Dynamic Model and Electro-Thermal-Mechanical Multi-Field Coupling Failure Analysis

Failure of insulated gate bipolar transistors (IGBTs) can make a serious impact on the entire rectification or inverter system. IGBTs are used in different practical applications, causing a large difference in the form of failure of its solder layer. Therefore, it is necessary to study the aging failure law of IGBT solder layer. Firstly, the improved IGBT dynamic model is used to build a three-phase rectifier circuit and correct its circuit power consumption error. Then constructing three-dimensional finite element model of IGBT and analyzing its chip temperature and solder layer stress distribution under electro-thermal-force multiphysics coupling. Finally, the randomly generated solder layer defects are used to investigate the effects of voids, cracks, etc. on solder layer failure, and the aging failure mechanism of the solder layer is obtained. The simulation results show that after the solder layer defect area ratio is higher than 15%, solder layer voids, cracks and shedding have a significant effect on chip junction temperature and solder layer stress. Among them, shedding and cracks have a greater influence on the stress of the solder layer.

Cooling Computer Chips with Cascaded and Non-cascaded Thermoelectric Devices

Thermoelectric devices are currently being used in cooling and generating electricity applications. This study mainly focuses on using thermoelectric devices for both applications towards cooling down computer chips; especially, that the very large scale integration technology has reached high advancement where more than 100 million transistors can be fabricated in 1 mm2. Reducing the non-uniformity of the chip temperature is important so as to decrease the induced thermal stress in this chip and consequently reduce its failure rate. To simultaneously reduce both the non-uniformity of the temperature distribution in the chip and the power requirements for the cooling system, thermoelectric generators can be installed on the cooler chip areas to harvest electrical power from the chip wasted heat. Thereafter, the chip hotspot areas are cooled down using thermoelectric coolers that are powered by the harvested electrical power from the thermoelectric generators in order to maintain the temperatures of these hotspots to be less than or equal a certain temperature threshold. Because no additional electrical power requirement is needed to cool down the hotspots, this cooling technique is called in this paper as “sustainable self-cooling framework for cooling chip hotspots”. However, the question is that can the harvested electrical power by the thermoelectric generators be enough to power the thermoelectric coolers for different computer chips at a given operating condition? As such, one of the objectives of this paper is to develop a three-dimensional numerical and optimization model to predict the thermal and electrical performance of cascaded and non-cascaded thermoelectric generators and cascaded and non-cascaded thermoelectric coolers for cooling chip applications. Then, validate the developed model against experimental data. The results showed that the predictions of the developed model were in good agreement with the experimental to within ± 4%. After gaining confidence in the developed model, it was used for a given chip operating condition to conduct a case study for a sustainable self-cooling framework in order to answer the raised question above. The results showed that the self-cooling framework can successfully cool down the hotspot at an acceptable temperature with not only no need for additional electrical power requirements but also for reducing the non-uniformity in the chip temperature distribution.

Performance optimization of cascaded and non-cascaded thermoelectric devices for cooling computer chips

Abstract Thermoelectric devices are currently being used in the applications of cooling and generating electricity. This study mainly focuses on using these devices for both applications toward cooling down computer chips. An important aspect in designing the cooling system is to minimize the non-uniformity of the temperature distribution in the computer chip so as to reduce the thermal stresses in it. Another aspect in designing the cooling system is to minimize its power requirements. To investigate these two aspects, the temperatures of the cold chip areas can be allowed to increase, but not to exceed a certain temperature threshold, by installing Thermoelectric Generators (TEGs) on these areas that can harvest electrical power from the chip wasted heat. Thereafter, the chip hotspot areas can be cooled down by installing Thermoelectric Coolers (TECs) on these areas that can be powered by the harvested electrical power from the TEGs in order to maintain the temperatures of these hotspots to be less than or equal a certain temperature threshold. This cooling technique is called “sustainable self-cooling framework” for cooling chip hotspots. However, the question is: can the harvested electrical power by the TEGs be enough to power the TECs for cooling chip hotspots? In this study, a 3D model is developed to optimize the performance of both TEGs and TECs. Thereafter, this model is validated against experimental data of TEC and TEG. The results showed that the model predictions were in good agreements with the experimental data to within ±4%. Also, considerations are given in this study to optimize the performance of cascaded and non-cascaded TEGs and TECs for future use them to develop sustainable self-cooling frameworks for cooling chip hotspots at different operating conditions. Finally, a case study is conducted in this paper for a sustainable self-cooling framework in order to address the question above. The results showed that the self-cooling framework can successfully cool down the hotspot at an acceptable temperature with not only no need for additional electrical power requirements but also for reducing the non-uniformity in the chip temperature distribution.

Thermal and Wirelength Optimization With TSV Assignment for 3-D-IC

3-D-IC is an emerging technology that overcomes the drawbacks of 2-D-IC and a vital structure called through-silicon via (TSV) is used to connect the adjacent layers vertically. In this paper, based on graph theories, we formulate the TSV assignment as an integer multicommodity min-cost (IMCMC) problem, and using multilevel algorithm, we get optimal solution. During the assignment, the capacity of the grid could be insufficient to contain the flows so that conditional grid extension effectively relieves the capacity limits and accelerate running speed. Thermal resistive model is introduced to simulate the heat dissipation of chip and estimate temperature distribution each layer. By inserting the thermal TSV, the temperature of superheated region is reduced. Moreover, considering about a more complicated situation, we propose a method to assign multipins in a net. The experimental results demonstrate our model in the IMCMC network using multilevel algorithm achieve optimized congestion, less wirelength, higher running speed, and reduced temperature.

A novel approach to thermal modeling based on three-dimensional analysis in turning Inconel 718 with round insert

The sharp increase of heat generated when processing difficult-to-machine materials is the main reason of short tool life and poor surface integrity. Temperature modeling plays a significant role in the mechanism of metal cutting, which can guide the optimization of cutting parameters. This paper proposes a modified three-dimensional analytical model of temperature prediction for oblique turning Inconel 718 with round carbide insert. The discretization of heat sources is indispensable to analyze the temperature rise due to the complicated geometry of uncut chip area. In this study, primary heat source (shear band) and secondary heat source (tool-chip interface) that divided into many increments through different discretization methods are considered to analyze thermal effects. For each increment of secondary heat source, the local contact length is calculated through a modified function considering global chip flow angle in oblique cutting. The local heat liberation intensities of primary and secondary heat sources are determined through analytical force prediction model. The variation of heat partition fraction with respect to immersion angle is given to study the characteristics of secondary heat source. Finally, a modified three-dimensional expression of temperature rises when turning with round insert considering semi-infinite medium is proposed based on classical thermal theory. The temperature distributions in chip, tool and workpiece can be determined through the proposed model. The results calculated through predictive model show good agreement with that given by finite element method (FEM) and experiments, which validates the correctness of the proposed model.

A Finite Element Modeling Prediction in High Precision Milling Process of Aluminum 6082-T6

This study investigates micro-end-milling machining prediction using three-dimensional finite element modeling method. The FE model was developed for contouring up-milling operation for prediction of chip flow, burr formation, cutting temperature and cutting forces in an integrated model. The flow stress behavior of the workpiece was modeled by the Johnson–Cook material constitutive model. Different cutting conditions were simulated to consider the effect of the process variables that might be difficult or impossible to follow in the physical experiments at this scale. The tool was precisely 3D modeled to describe the detailed geometry of the tool which is one of the critical aspects of the model and is characteristic of the cutter tool micro-geometry design. Furthermore, the tool deflection was studied using a FE model under the experimental cutting forces measured in the different cutting conditions in order to consider the micro-end-mill deviation from the nominal position. 3D simulations of chip flow and temperature distribution are compared in various cutting conditions. The results of the burr formation, temperature distribution and cutting forces in three directions predictions are compared against the experiments. Simulations were able to predict the burr height with an accuracy between 1 and 4 µm depending on cutting parameters settings. The results of this study are beneficial to comprehend the micro-end-milling chip and burr formation to increase the machinability of the workpiece and to understand the influence of cutting parameter in order to prevent several experimental tests prior to the final machining.

Implementation of direct Chip junction temperature measurement in high power IGBT module in operation — Railway traction converter

Reliability and lifetime of high power IGBT multichip modules used in railway traction converters is key for traction manufacturers to meet operators requirements. High power IGBT multichip modules used today in railway traction are (sub) systems containing a (large) number of paralleled chips. Temperature distribution between paralleled chips in the module may induce predominant effects on performances and operational reliability. This paper presents an experimental set-up based on optical fibers to measure individual chip temperatures of a 6500 V – 750 A IGBT module during converter operation in real conditions of power and voltage. This set-up was used to study chip temperature distribution within high power IGBT multichip modules during different phases of converter operation and cooling conditions. It is also used to evaluate and validate different approaches of condition and health monitoring advanced functions based on indirect temperature measurements coupled with electro-thermal models.

Study on thermal effects of InSb infrared focal plane arrays irradiated by pulsed laser

To learn thermal effects of InSb infrared focal plane arrays (IRFPAs) detector irradiated by pulsed laser, basing on ANSYS software, and considering temperature dependent thermal parameters of InSb, a three dimensional temperature field analysis model of InSb IRFPAs detector by 1064 nm Gauss laser irradiation is built. The characteristics of temperature rise and temperature distribution in InSb IRFPAs detector are studied. The results show that the maximum temperature always occurs in InSb chip, locating at the top layer of InSb IRFPAs detector, the temperature rises in each layer are different, and the temperature distribution in InSb IRFPAs detector is quite different from that in single-layer material. The temperature distribution of InSb chip in InSb IRFPAs reduces from center to outside, while it shows not a smooth decrease, but a concentric-ringed ripple decrease with non-consecutive high temperature extremum regions. The temperature distribution patterns in underfill, Si readout integrated circuits are similar to that in InSb chip, but the discontinuous high temperature areas in InSb chip, underfill locate at the regions between indium bumps, and the discontinuous high temperature areas in Si readout integrated circuits locate at the contact area with indium bumps. This different temperature distribution phenomenon in each material is mainly due to its multi-layer architecture and quite different thermal properties of the middle layer, which is an interlacing layout of underfill and indium bumps. Besides, the influences of indium bump structure size on the temperature rise are also discussed. All these results qualitatively reflect the disciplines of temperature rise in InSb IRFPAs detector, providing a theory support for thermal analysis of detectors irradiated by laser.