Circuit Techniques Research Articles

Radiation hard true single-phase-clock logic for high-speed circuits in 28 nm CMOS

True Single-Phase-Clock (TSPC) dynamic logic is widely used in high-speed circuits such as high-speed SERDES (Serializer/Deserializer) and frequency dividers. TSPC flip-flops (FF) are known for their high operational speed and low power consumption, compared to static FFs. Due to the relatively high leakage currents in modern CMOS processes, the use of leakage protection techniques of the storage nodes in TSPC must be considered, especially at high radiation doses. In this paper, the limitations originating from Total Ionization Dose (TID)-induced subthreshold leakage currents are analysed and radiation-hardening-by-design (RHBD) circuit techniques are proposed. Additionally, Single Event Upsets (SEU) are investigated by quantifying the critical charge of the leakage protected TSPC FF. The results are compared to both the static and the TSPC FF without leakage mitigation.

ПРИМЕНЕНИЕ ИНСЕЙФИНГА ДЛЯ АНАЛИЗА БИЗНЕС-ПРОЦЕСОВ В ОРГАНИЗАЦИИ

Insafing allows you to form and discuss tasks from the field of science, education, design. Insafing is understood as an intelligent interactive communication technology that begins to form on the basis of the theory of dynamic information systems. Thus, insafing, as a TDIS application, has a great potential for visualizing our activity, generalizing traditional circuit techniques due to the presence of special rules, structures and its own language for reengineering and optimizing business processes. The article discusses the use of insafing for the analysis of business processes, highlighting the processes that the owner should control and optimize directly. As a result of the use of insafing for the analysis and optimization of business processes of the organization, triads were obtained that allow determining the success factors of an economic entity in the modern economy. These are qualified personnel, decent remuneration, division of management into tactical and strategic levels, developed channels of information exchange and intangible motivation.

Convolutional Codec Implemented by Genetic Circuits for Molecular Communication.

Molecular communication (MC), which transmits information through molecules, has emerged as a promising technique to enable communication links between nanomachines. To establish information transmission using molecules, synthetic biology through genetic circuits techniques can be utilized to construct biological components. Recent efforts on genetic circuits have produced many exciting MC systems and generated substantial insights. With basic gene regulatory modules and motifs, researchers are now constructing artificial networks with novel functions that will serve as building blocks in the MC system. In this paper, we investigate the design of genetic circuits to implement the convolutional codec in a diffusion-based MC channel with the concentration shift keying (CSK) transmission scheme. At the receiver, a majority-logic decoder is applied to decode the received symbols. These functions are completely realized in the field of biochemistry through the activation and inhibition of genes and biochemical reactions, rather than through classical electrical circuits. Biochemical simulations are used to verify the feasibility of the system and analyze the impairments caused by diffusion noise and chemical reaction noise of genetic circuits.

Design Of Three Stage Comparator Using 90nm Technology

In this paper, the design of three stage comparator using 90nm technology is presented. The comparator is one of the block that limits the speed of the converter, its optimization is crucial and important and design of Analog-to-Digital Converter (ADC),is the speed limiting element in comparator. It describes the schematic design of a three stage CMOS comparator to achieve lower power dissipation and a lower offset voltage, with high-speed operation. Test structure of the comparator are designed using GPDK 90nm. The three-stage comparator makes it possible to use NMOS input pairs in both the regeneration stage and the amplification stage, further increasing the speed. Furthermore, in the modified version of three-stage comparator, a CMOS input pair is adopted at the amplification stage. Simulation results are obtained and it shows that the proposed design can work under 1.8V supply, with an offset voltage of 200mV, and thus, an innovative circuit technique is implemented to overcome these limitations. The work carried out is the mini-project that is a part & parcel of the curriculum in the 2nd semester.

A 10-MHz 85.1-dB SFDR 1.1-mW continuous-time Delta–sigma modulator employing calibration-free SC DAC and passive front-end low-pass filter

This article demonstrates the circuit technique of a highly power-efficient continuous-time (CT) Delta–sigma modulator (DSM) based on a switched-capacitor (SC) feedback digital-to-analog converter (DAC) and a passive front-end low-pass filter (LPF). The technique addresses the clock sensitivity issue of conventional DACs while maintaining the alias rejection. It is validated by a fourth-order CT DSM prototype fabricated in 65-nm CMOS technology. The input stage of the DSM is an active-RC integrator merged with a passive front-end LPF. A resonator follows and realizes the cascade of resonators with feedforward (CRFF) structure. The accurate feedback loop employs a highly linear and calibration-free 5-level SC DAC. Based on the linear periodically time-varying (LPTV) system model, an exact analysis is given to explain the effects of the passive LPF and SC DAC combo on the signal transfer function (STF), and hence, on the alias rejection. The prototype DSM achieves a 70.2-dB signal to noise and distortion ratio (SNDR) and an 85.1-dB spurious-free dynamic range (SFDR) in a 10-MHz bandwidth, while dissipating 1.1 mW with a 1-V supply. The modulator achieves a 65.4-dB alias rejection and confirms the closed-form analytical results.

A Neoteric Approach for Logic with Embedded Memory Leveraging Crosstalk Computing

One of the essential elements of computing is the memory element. Flip-flops form an integral part of a System-on-Chip (SoC) and consume most of the area on the die. To meet the high-speed performance demands by the data-intensive applications such as artificial intelligence, cloud computing, and machine learning, we propose to integrate memory with the logic to get built-in memory Logic circuits that operate based on the crosstalk computing logic. These circuits are called Crosstalk Built-in Memory Logic (CBML) circuits, which exploit the detrimental interconnect crosstalk and astutely turn this unwanted effect into a computing principle with embedded memory. By virtue of our novel CBML circuit technique, the logic is computed, and the result is stored intrinsically within these complex circuits. The stored values will be retained irrespective of the change in input until the next logic evaluation cycle. This neoteric embedding of memory in logic provides high-speed operation with a reduced number of transistors. In this article, we have manifested the built-in memory feature of the complex CBML circuits using 16 nanometer (nm) PTM models in HSPICE. Benchmarking is performed by comparing with the equivalent static CMOS circuits to compare the number of transistors, power, and performance. It is observed that the number of transistors consumed by CBML 4-bit Full-Adder (the key element prevalent in Arithmetic circuits, e.g., ALU, Counters) is up to 46% less, and performance is improved by 27% over the equivalent CMOS circuits. This circuit serves as an example of a large-scale CBML circuit. Also, the performance improvement achieved by other circuits such as 3-input AND and the CARRY logic is up to 60% along with a 40% reduction in the number of transistors. CBML circuits have the potential to pave the way for special high-speed macros with specifically engineered structures.

An Ultra High Step-Up Dual-Input Single-Output DC–DC Converter Based on Coupled Inductor

This article introduces a new coupled inductor based dual-input ultra-high step-up dc–dc converter with a high voltage conversion ratio, low voltage stress across semiconductor components, and high efficiency features. The coupled inductor and voltage multiplier circuit (VMC) techniques have been utilized to enhance the voltage gain. The blocking voltages of power switches are clamped by VMC at low values and can be controlled via the turn ratio of the coupled inductors that decreases the voltage rate of power switches and converter's cost. The presented dual-input structure can transfer power to the load from two independent voltage sources. Besides, the inputs and output ports are common ground, which can reduce the electromagnetic interference influences. Operation modes delineation, steady-state analysis, and comparison section are provided for describing the proposed structure performance. Finally, to confirm the effectiveness of the presented topology, experimental waveforms with a 200 W output power at 50 kHz switching frequency are presented.

New partitioned domino circuit for power-efficient wide gates

In this article, a new domino circuit is presented to decrease the power consumption of wide gates without considerable performance and robustness degradation. The suggested circuit technique modifies the output inverter to decrease the switching power by decreasing the voltage swing. Moreover, the wide pull-down networks can be partitioned into smaller networks. To merge the partitioned pull-down networks, a dynamic NAND gate is employed to increase the circuit performance. Using the proposed technique, the leakage current is decreased in the wide gates because of the stacking effect. Also, the noise immunity is improved due to the body effect. The wide OR gates are simulated in 90-nm CMOS technology. Simulation results show 54% power reduction and 2.55 times improvement in the noise immunity at the same speed in comparison with the conventional circuit technique for 64-input OR gates. In addition, a 128-input AND-OR gate is designed using the proposed circuit. Results demonstrate that power and delay are reduced by 39% and 11%, respectively, compared to the conventional AND-OR gate at the same robustness.

Optimal Design of Permanent Magnet Synchronous Machine Based on Random Walk Method and Semi 3D Magnetic Equivalent Circuit Considering Overhang Effect

Permanent magnet synchronous machines (PMSMs) with an overhang structure can increase power density by compensating for the increased magnetic energy of permanent magnets. To analyze the overhang structure, a three-dimensional (3D) analysis of PMSMs is essential. However, 3D analysis takes a long time and the modeling process is complicated in the initial design stage. To overcome these problems, a magnetic equivalent circuit technique is applied to the 2D model. In this paper, an optimal design method for PMSMs with an overhang structure is proposed based on the semi 3D magnetic equivalent circuit (MEC) and random walk method. By using semi 3D MEC, it is possible to quickly analyze PMSM and obtain accurate electromagnetic analysis results considering the overhang effect. Moreover, the volume and weight of PMSM can be minimized by optimizing the rotor’s four design parameters using a random walk algorithm. To obtain high efficiency, the objective function is selected so that copper loss is minimized under the same constraints. The validity of the proposed design technique is verified by comparing the analysis results of semi 3D MEC and 3D finite element method for the derived optimal model.

A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency

Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance ([Formula: see text]) is the main dominant source of frequency and gain ([Formula: see text]) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates [Formula: see text] times variation in [Formula: see text] across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5[Formula: see text]GHz is developed in 65[Formula: see text]nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum [Formula: see text] variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4[Formula: see text]mW power from 1[Formula: see text]V power supply.

Modification of the CSIRO method in the long-term monitoring of slope-induced stress

The in situ stress measurement technique can be used in long-term monitoring of induced stress to obtain three-dimensional stress states in slope engineering. In the monitoring, the ambient temperature fluctuation, “zero” drift of the logging data, and stable power supply should be considered. A dual temperature compensation circuit and experimental calibration techniques are proposed to increase accuracy based on the principle of the CSIRO method and considering the effect of a long-term disturbance of temperature in slope engineering. In view of the characteristics of the stress field distribution of the slope rock, the strain gauge layout scheme for induced stress monitoring of slope rock is modified to achieve the acquisition of three parallel measurements at one measurement and a stress–strain relationship equation for multilayer elastic layers is derived. An in situ stress logging system with the function of transient logging and data-connection in power cut condition is introduced to achieve a continuous correlation of measurement data under power cut conditions. An online cloud platform is established for the slope engineering of Au Mountain Iron Mine in Maanshan City. The results show that the data deviation of logging system is ±14 με with 24 days’ power off, and errors with amount of 15% were corrected by the dual temperature compensation method. The remotely transmitted data reflect the effect of temperature changes and the evolution of strain (induced stress) in real time to satisfy the demand of long-term monitoring of slope engineering.

High-Precision Thickness Measurement of Cu Film on Si-Based Wafer Using Erasable Printed Eddy Current Coil and High-Sensitivity Associated Circuit Techniques

The eddy current coil is widely adopted to measure the thickness of copper (Cu) film on the silicon (Si) based wafer. However, the lift-off distance (LOD) variation between the coil and Cu film has a strong negative effect on the accuracy and repetitiveness of the thickness measurement. Therefore, it is necessary to eliminate the impact of LOD variation. In this article, a high-precision thickness measurement method is proposed to determine the thickness of Cu film on the Si-based wafer by using the techniques of the erasable printed eddy current coil (EPECC) and the high-sensitivity associated circuit. The theoretical feasibility and sensitivity improvement of the conceptual design are analyzed in detail. As a proof of concept, a prototype of the proposed method is fabricated. The EPECC is prepared on the back surface of the wafer, and the LOD is unvaried during the measurement. Experimental results show that comparing with the traditional eddy current coil, the measurement stability, precision, and accuracy of the Cu film thickness by the proposed method are significantly improved even under severe vibration conditions. The relative error is 2% in repeated measurements.

A 28 nm 512 Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for high density and low BER cryptographic key in IoT devices

This paper elaborates a 2-transistor -2-resistor (2T2R) RRAM PUF scheme with assisting circuit techniques for dense and reliable cryptographic key generation and storage. The set time mismatch in two adjacent RRAM devices is utilized to enhance the tolerance of PUF output for against PVTA variations. Array architecture with interleaved cell mirroring further improves the randomness by eliminating the systematic deviation. Self-adaptive write with current limiter eliminates the negative effect of mismatch in the peripheral circuits and suppresses the undue duration of large operation current. Double-ended differential sensing brings robustness against side-channel attacks and less voltage stress on RRAM cells. Silicon data from a 512 Kb RRAM PUF test chip in 28 nm technology demonstrates our PUF passes NIST test with intra-chip Hamming distance (HD) of <10−5 and inter-chip HD of 0.496, and the BER is < 10−5 from 0 to 120 °C. The proposed PUF also supports reconfigurability with good randomness and improved efficiency, featuring good resilience against machine learning attacks.

Circuit Techniques to Improve Low-Light Characteristics and High-Accuracy Evaluation System for CMOS Image Sensor.

The surveillance cameras we focus on target the volume zone, and area reduction is a top priority. However, by simplifying the ADC comparator, we face a new RUSH current issue, for which we propose a circuit solution. This paper proposes two novel techniques of column-ADC for surveillance cameras to improve low-light characteristics. RUSH current compensation reduces transient current consumption fluctuations during AD conversion and utilizing timing shift ADCs decreases the number of simultaneously operating ADCs. These proposed techniques improve low-light characteristics because they reduce the operating noise of the circuit. In order to support small signal measurement, this paper also proposes a high-accuracy evaluation system that can measure both small optical/electrical signals in low-light circumstances. To demonstrate these proposals, test chips were fabricated using a 55 nm CIS process and their optical/electrical characteristics were measured. As a result, low-light linearity as optical characteristics were reduced by 63% and column interference (RUSH current) as an electrical characteristic was also reduced by 50%. As for the high-accuracy evaluation system, we confirmed that the inter-sample variation of column interference was 0.05 LSB. This ADC achieved a figure-of-merit (FoM) of 0.32 e-·pJ/step, demonstrating its usefulness for other ADC architectures while using a single-slope-based simple configuration.

Prevention, Mitigation and Correlative Acoustic Spectroscopy of Lithium-Ion Battery Thermal Runaway

Scrutiny of lithium-ion battery failure has seen heavy regulations and restrictions with well-reported headlines of catastrophic thermal runaway of commercial electronic devices and electric vehicles. Thermal runaway occurs at a critical temperature when the rate of heat generation exceeds that of dissipation, highly exothermic decomposition reactions occur and temperatures in excess of 600 ᵒC can be measured 1. These concerns continue to grow with applications of greater energy density and capacity, such as the proliferation of electric vehicles.Isolation of electronically conductive components within the electrode assembly to prevent short circuit has shown promise to prevent the onset of thermal runaway within lithium-ion cells. Here 2, the authors present a metal-coated polymer current collector (PCC) and thermally stable separator (TSS) to prevent and mitigate thermal runaway. 2.10 Ah capacity 18650-geometry cells were subject to thermal, internal short circuit and nail penetration abuse techniques with these materials and their commercial counterparts for individual comparison of the PCCs and TSS. Reductions in cell mass were observed on the order of 5%, due to the majority of the PCC consisting of the polymer substrate rather than pure aluminium and copper in commercial current collectors. High speed synchrotron facilities provided insights into the function of the polymer current collectors with post- mortem X-ray computed tomography. During mitigation testing, cells were taken to failure with thermal and with an internal short circuit device (ISCD) within a Fraction Thermal Runaway Calorimeter (FTRC) to measure the reduction in calorific output. This highlighted the difficulty that exists with detecting gas-induced and internal structural degradation within lithium-ion batteries, especially outside specialized diagnostic laboratories to characterize these rapid changes with elapse within seconds. Attenuation and wave velocity determined by the propagative properties of ultrasound through different phases, prominently highlights structural, temperature and formation of different phases which occur during thermal runaway. Such analysis provided by acoustic spectroscopy are characterised by variations in the attenuation and signal peak shifts. Further information which can be derived from spatial mapping using acoustic spectroscopy 3,4 include: state of charge, state of health, electrochemical performance.Cells made with the aluminium-coated PCC demonstrated 100% success in prevention of thermal runaway during nail penetration, retaining a voltage above 4.00 V. Cells manufactured with the PCC, both PCC and TSS, exhibited a reduction in total energy output on average of 19.4% and 41.3% respectively during thermal abuse. ISCD triggered thermal runaways also observed reductions of 24.6% and 30.3% with these respective cell material configurations. Prevention of thermal runaway is a transformative advancement in improving lithium-ion battery safety, especially in the cylindrical 18650-format cell. Additionally, significant reductions in the calorific output during failure were measured. These safety innovations provides efficacy of these materials independent of cell chemistry (provided they are stable in the operating environment) while also increasing the energy density and be assimilated into existing manufacturing technology.Furthermore, the authors demonstrate correlative high-speed acoustic spectroscopy during routine cycling of a commercial 210 mAh lithium-ion pouch cell and during thermal abuse 5. Mechanical deformation such as gas-induced delaminations, which have been linked to degradation in electrochemical performance, capacity retention, cell state of health and impending thermal runaway, were detected. This degradation was observed with characteristic acoustic spectroscopy signal peaks changes during cycling due to cell manufacturing defects and during induced thermal abuse, were corroborated with high speed synchrotron X-ray imaging. This analysis can be observed immediately after application of the acoustic probe which emphasises the rapid diagnostics insights provided by acoustic spectroscopy as a robust field deployable technique. Thus, integration into battery management systems, second-life evaluation/recycling or as in-line cell metrology during manufacturing would provide real time direct insight into these metrics. Finegan DP, Darcy E, Keyser M, et al. Identifying the Cause of Rupture of Li-Ion Batteries during Thermal Runaway. Adv Sci. 2018. doi:10.1002/advs.201700369Pham MTM, Darst JJ, Walker WQ, et al. Prevention of lithium-ion battery thermal runaway using polymer-substrate current collectors. Cell Reports Phys Sci. 2021. doi:10.1016/j.xcrp.2021.100360Robinson JB, Pham M, Kok MDR, Heenan TMM, Brett DJL, Shearing PR. Examining the Cycling Behaviour of Li-Ion Batteries Using Ultrasonic Time-of-Flight Measurements. J Power Sources. 2019;444.Robinson JB, Maier M, Compton T, Alster G, Brett DJL, Shearing PR. Spatially resolved ultrasound diagnostics of Li-ion battery electrodes. Phys Chem Chem Phys. 2018. doi:10.1039/c8cp07098aPham MTM, Darst JJ, Finegan DP, et al. Correlative acoustic time-of-flight spectroscopy and X-ray imaging to investigate gas-induced delamination in lithium-ion pouch cells during thermal runaway. J Power Sources. 2020;470:228039. doi:10.1016/j.jpowsour.2020.228039

Dual-Band Design Techniques for Microwave Passive Circuits: A Review and Applications

The introduction of new technology in the wireless communication industry increases the number of frequency bands in the communication environment. Therefore, a communication system capable of functioning over several frequency bands, known as a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">multiband communication system</i> , is required. In addition, multiband communication systems support technology upgrades by smoothly bridging the migration from the existing technology to a newer technology. A multiband communication system can be developed with the help of two approaches. The first approach is a multiband communication system that contains multiple microwave circuits, with each circuit optimized for a single band; for example, a dual-band communication system has two low-pass filters and two power amplifiers. But this approach increases not only the size but also the cost of the system. In the second approach, rather than using a separate power amplifier and filter for each frequency band, a single power amplifier, filter, and other components are used that can support more than one frequency band. These circuits are known as <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">multiband microwave circuits</i> . Multiband circuits not only minimize size but also reduce the cost of designing the multiband communication system.

Proposal and analysis of carbon nanotube based differential multibit through glass vias

The paper proposes glass as a potential material to advanced interposers for high-density three-dimensional (3-D) integration. On the basis of multi-bit through glass via (TGV) which comprises of TGVs filled with multi-walled carbon nanotubes (MWCNTs)/single-walled CNTs (SWCNTs) and separate conducting pads, the design of novel differential multibit-CNT TGVs (DM-TGCVs) is proposed and studied. The effective complex conductivity is formulated for accurate characterization of the high frequency behaviour of DM-TGCVs. A distributed π-type transmission line model for the modeling of DM-TGCVs is established and the frequency dependent impedance is extracted through partial element equivalent circuit (PEEC) technique. The influence of CNT filling ratio, probability of metallic fraction of CNTs, and CNTs as filler material on the resistance and inductance is also studied. Through the proposed analytical model, signal insertion loss of DM-TGCVs in the differential- and common-mode configurations is exhaustively investigated. Due to ultra-high electrical resistivity of glass (1012 − 1016 Ω-cm), signal loss in DM-TGCVs is determined by the conductor loss, which results in an improved electrical performance under differential-mode signaling than common-mode signaling approach. This phenomenon is unique to TGVs and totally different from the conventional through silicon vias, where signal loss is dominated by the dielectric loss at high frequencies. The magnitude of insertion loss (S21) for the proposed DM-TGCVs under differential-mode configuration w.r.t. differential TSVs (D-TSVs) and differential multibit CNT TSVs (DMC-TSVs) improves up to ∼ 44% and ∼22%, respectively for varying via radius. The DM-TGCVs also exhibit superior crosstalk inhibition capability and provide up to ∼89% and ∼24% improvements in crosstalk than D-TSVs and DMC-TSVs at f = 20 GHz. More importantly, DM-TGCVs provide one-third saving of the chip area compared to D-TSVs.

Circuit Techniques for High Efficiency Piezoelectric Energy Harvesting.

This brief presents a tutorial on multifaceted techniques for high efficiency piezoelectric energy harvesting. For the purpose of helping design piezoelectric energy harvesting system according to different application scenarios, we summarize and discuss the recent design trends and challenges. We divide the design focus into the following three categories, namely, (1) AC-DC rectifiers, (2) CP compensation circuits, (3) maximum power point tracking (MPPT) circuits. The features, problems encountered, and suitable systems of various AC-DC rectifier topologies are introduced and compared. The important role of non-linear methods for piezoelectric energy harvesting is illustrated from the perspective of impedance matching. Energy extraction techniques and voltage flipping techniques based on inductors, capacitors, and hybrid structures are analyzed. MPPT techniques with different features and targets are discussed.

Miniaturization for wearable EEG systems: recording hardware and data processing.

As more people desire at-home diagnosis and treatment for their health improvement, healthcare devices have become more wearable, comfortable, and easy to use. In that sense, the miniaturization of electroencephalography (EEG) systems is a major challenge for developing daily-life healthcare devices. Recently, because of the intertwined relationship between EEG recording and processing, co-research of EEG recording hardware and data processing has been emphasized for whole-in-one miniaturized EEG systems. This paper introduces miniaturization techniques in analog-front-end hardware and processing algorithms for such EEG systems. To miniaturize EEG recording hardware, various types of compact electrodes and mm-sized integrated circuits (IC) techniques including artifact rejection are studied to record accurate EEG signals in a much smaller manner. Active electrode and in-ear EEG technologies are also researched to make small-form-factor EEG measurement structures. Furthermore, miniaturization techniques for EEG processing are discussed including channel selection techniques that reduce the number of required electrode channel and hardware implementation of processing algorithms that simplify the EEG processing stage.

STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks

This paper presents a novel architecture for in-memory computation of binary neural network (BNN) workloads based on STT-MRAM arrays. In the proposed architecture, BNN inputs are fed through bitlines, then, a BNN vector multiplication can be done by single sensing of the merged SL voltage of a row. Our design allows to perform unrestricted accumulation across rows for full utilization of the array and BNN model scalability, and overcomes challenges on the sensing circuit due to the limitation of low regular tunneling magnetoresistance ratio (TMR) in STT-MRAM. Circuit techniques are introduced in the periphery to make the energy-speed-area-robustness tradeoff more favorable. In particular, time-based sensing (TBS) and boosting are introduced to enhance the accuracy of the BNN computations. System simulations show 80.01% (98.42%) accuracy under the CIFAR-10 (MNIST) dataset under the effect of local and global process variations, corresponding to an 8.59% (0.38%) accuracy loss compared to the original BNN software implementation, while achieving an energy efficiency of 311 TOPS/W.