Tasks In Pipeline Research Articles

Enhanced computational performance of the lattice Boltzmann model for simulating micron- and submicron-size particle flows and non-Newtonian fluid flows

Significant improvements in the computational performance of the lattice-Boltzmann (LB) model, coded in FORTRAN90, were achieved through application of enhancement techniques. Applied techniques include optimization of array memory layouts, data structure simplification, random number generation outside the simulation thread(s), code parallelization via OpenMP, and intra- and inter-timestep task pipelining. Effectiveness of these optimization techniques was measured on three benchmark problems: (i) transient flow of multiple particles in a Newtonian fluid in a heterogeneous fractured porous domain, (ii) thermal fluctuation of the fluid at the sub-micron scale and the resultant Brownian motion of a particle, and (iii) non-Newtonian fluid flow in a smooth-walled channel. Application of the aforementioned optimization techniques resulted in an average 21× performance improvement, which could significantly enhance practical uses of the LB models in diverse applications, focusing on the fate and transport of nano-size or micron-size particles in non-Newtonian fluids.

Comparing Bar Chart Authoring with Microsoft Excel and Tangible Tiles

AbstractProviding tools that make visualization authoring accessible to visualization non‐experts is a major research challenge. Currently the most common approach to generating a visualization is to use software that quickly and automatically produces visualizations based on templates. However, it has recently been suggested that constructing a visualization with tangible tiles may be a more accessible method, especially for people without visualization expertise. There is still much to be learned about the differences between these two visualization authoring practices. To better understand how people author visualizations in these two conditions, we ran a qualitative study comparing the use of software to the use of tangible tiles, for the creation of bar charts. Close observation of authoring activities showed how each of the following varied according to the tool used: 1) sequences of action; 2) distribution of time spent on different aspects of the InfoVis pipeline; 3) pipeline task separation; and 4) freedom to manipulate visual variables. From these observations, we discuss the implications of the variations in activity sequences, noting tool design considerations and pointing to future research questions.

The Design and Implementation of TIDeFlow: A Dataflow-Inspired Execution Model for Parallel Loops and Task Pipelining

This paper provides an extended description of the design and implementation of the Time Iterated Dependency Flow (TIDeFlow) execution model. TIDeFlow is a dataflow-inspired model that simplifies the scheduling of shared resources on many-core processors. To accomplish this, programs are specified as directed graphs and the dataflow model is extended through the introduction of intrinsic constructs for parallel loops and the arbitrary pipelining of operations. The main contributions of this paper are: (1) a formal description of the TIDeFlow execution model and its programming model, (2) a description of the TIDeFlow implementation and its strengths over previous execution models, such as the ability to natively express parallel loops and task pipelining, (3) an analysis of experimental results showing the advantages of TIDeFlow with respect to expressing parallel programs on many-core architectures and (4) a presentation of the implementation of a low overhead runtime system for TIDeFlow.

Divide‐and‐conquer approach for solving singular value decomposition based on MapReduce

SummarySingular value decomposition (SVD) shows strong vitality in the area of information analysis and has significant application value in most of the scientific big data fields. However, with the rapid development of Internet, the information online reveals fast growing trend. For a large‐scale matrix, applying SVD computation directly is both time consuming and memory demanding. There are many works available to speed up the computation of SVD based on the message passing interface model. However, to deal with large‐scale data processing, a MapReduce model has many advantages over a message passing interface model, such as fault tolerance, load balancing and simplicity. For a MapReduce environment, existing approaches only focus on low rank SVD approximation and tall‐and‐skinny matrix SVD computation, and there are no implementations of full rank SVD computation. In this paper, we propose a MapReduce‐based implementation for solving divide‐and‐conquer SVD algorithm. To achieve high performance, we design a two‐stage task scheduling strategy based on the mathematical characteristics of divide‐and‐conquer SVD algorithm. To further strengthen the performance, we propose a row‐index‐based divide algorithm, a pipelined task scheduling method, and revised block matrix multiplication in MapReduce framework. Experimental result shows the efficiency of our algorithm. Our implementation can accommodate full rank SVD computation of large‐scale matrix very efficiently. Copyright © 2014 John Wiley & Sons, Ltd.

PARAMO: A PARAllel predictive MOdeling platform for healthcare analytic research using electronic health records

ObjectiveHealthcare analytics research increasingly involves the construction of predictive models for disease targets across varying patient cohorts using electronic health records (EHRs). To facilitate this process, it is critical to support a pipeline of tasks: (1) cohort construction, (2) feature construction, (3) cross-validation, (4) feature selection, and (5) classification. To develop an appropriate model, it is necessary to compare and refine models derived from a diversity of cohorts, patient-specific features, and statistical frameworks. The goal of this work is to develop and evaluate a predictive modeling platform that can be used to simplify and expedite this process for health data. MethodsTo support this goal, we developed a PARAllel predictive MOdeling (PARAMO) platform which (1) constructs a dependency graph of tasks from specifications of predictive modeling pipelines, (2) schedules the tasks in a topological ordering of the graph, and (3) executes those tasks in parallel. We implemented this platform using Map-Reduce to enable independent tasks to run in parallel in a cluster computing environment. Different task scheduling preferences are also supported. ResultsWe assess the performance of PARAMO on various workloads using three datasets derived from the EHR systems in place at Geisinger Health System and Vanderbilt University Medical Center and an anonymous longitudinal claims database. We demonstrate significant gains in computational efficiency against a standard approach. In particular, PARAMO can build 800 different models on a 300,000 patient data set in 3h in parallel compared to 9days if running sequentially. ConclusionThis work demonstrates that an efficient parallel predictive modeling platform can be developed for EHR data. This platform can facilitate large-scale modeling endeavors and speed-up the research workflow and reuse of health information. This platform is only a first step and provides the foundation for our ultimate goal of building analytic pipelines that are specialized for health data researchers.

Space optimal solution for data reordering in streaming applications on NoC based MPSoC

Many streaming applications feature coarse grain task farm or pipeline parallelism and can be modeled as a set of parallel threads. Performance requirements can often only be met by mapping the application onto a Multi Processor System-on-Chip (MPSoC). To avoid contention, hierarchical interconnection networks, where the central interconnect is a network-on-chip, are employed. In such a clustered MPSoC, the memory access latency varies strongly depending on the location of data, and is the principal cause of out-of-order arrival of data items. We present an algorithm which re-establishes the order of data items on the output side. If their earliness or lateness exceeds a limit previously fixed by experimentation, they are dropped, otherwise stored in a buffer. Write operations to this buffer are random access, whereas read operations are in FIFO order. Our algorithm guarantees that no data is removed from the buffer before it has been read, and, for a given throughput, minimum buffer size. The algorithm was implemented within the output co-processors for three application case studies and validated on a simulation platform based on the SoCLib library.

Comments: Young Technology Showcase

Editor's column This month, JPT publishes the first articles in its new Young Technology Showcase section. The articles in this and subsequent issues will spotlight the best in “young technology”—technology new in the development-to-adoption cycle that shows great promise for use in the upstream oil and gas industry. Although hydrocarbons supply is abundant, global energy demand is growing steadily and producing these resources is becoming more complex and technically challenging. Many of these assets reside in difficult locations and in extreme environments. The most advanced technologies, some yet to be developed, will be required to find, produce, and maintain these resources. And although the oil and gas industry excels in the use of high-tech tools and techniques, it is relatively slow in adopting new technologies compared with other industries. In concert with SPE’s role to disseminate technical information to the upstream sector, the SPE Board of Directors created a task force to examine how the society could help accelerate the acceptance and awareness of new upstream technology. SPE transfers information about more mature technology through its many publications, conferences, lectures, and workshops. But highlighting a young technology new in the development cycle often does not lend itself to technical papers. The SPE Technical Directors’ Technology Pipeline Task Force aims to accelerate emerging technology through publications and other vehicles and is working with JPT on its initial initiative to publicize promising new technology. The committee has been reviewing submissions sent in by both large and small technology developers and providers. The two technologies highlighted in this issue are a new stage multiplier device created by Packers Plus and Boots & Coots Power Reach Service that combines the features of coiled tubing and jointed tubing in well intervention. Other technologies have been approved by the committee as having great potential will be published in upcoming issues of JPT. The committee is in the process of reviewing numerous others. Among the technologies being reviewed are aspects of robotics, drilling methods, sand management, and fracturing. In the meantime, JPT and the committee will continue to welcome submissions of young technology for possible publication. Companies and individuals are invited to submit information on their new technologies by submitting a template that describes the technology and what it can do, which is available at www.jptonline.org/index. php?id=986. Developers of technology will need to define the reason or need for the technology, verify its purpose, describe how it works, state its target applications, and note how and where it has been used. In addition, the submission must provide information on any case studies, discuss what would cause the new technology to not work or fail, and describe the possible health, safety, and environmental impact. The technology must provide significant benefits beyond commonly used technologies. It must also be original and, to a certain degree, groundbreaking. If you are interested in submitting information on your new technology or have any questions about this process, please contact me at jdonnelly@spe.org.

Event-based parareal: A data-flow based implementation of parareal

Parareal is an iterative algorithm that, in effect, achieves temporal decomposition for a time-dependent system of differential or partial differential equations. A solution is obtained in a shorter wall-clock time, but at the expense of increased compute cycles. The algorithm combines a fine solver that solves the system to acceptable accuracy with an approximate coarse solver. The critical task for the successful implementation of parareal on any system is the development of a coarse solver that leads to convergence in a small number of iterations compared to the number of time slices in the full time interval, and is, at the same time, much faster than the fine solver. Very fast coarse solvers may not lead to sufficiently rapid convergence, and slow coarse solvers may not lead to significant gains even if the number of iterations to convergence is satisfactory. We find that the difficulty of meeting these conflicting demands can be substantially eased by using a data-driven, event-based implementation of parareal. As a result, tasks for one iteration do not wait for the previous iteration to complete, but are started when the needed data are available. For given convergence properties, the event-based approach relaxes the speed requirements on the coarse solver by a factor of ∼K, where K is the number of iterations required for a converged solution. This may, for many problems, lead to an efficient parareal implementation that would otherwise not be possible or would require substantial coarse solver development. In addition, the framework used for this implementation executes a task when the data dependencies are satisfied and computational resources are available. This leads to improved computational efficiency over previous approaches that pipeline or schedule groups of tasks to a particular processor or group of processors.

Study on Real-Time Response Efficiency of Task Pipeline Based on Multi- Core Systems

Study on Real-Time Response Efficiency of Task Pipeline Based on Multi- Core Systems

Comments: Highlighting New Technology

Editor's column Last year, the SPE Board of Directors created a task force headed by its technical directors to examine how the society could help accelerate the acceptance and awareness of new upstream technology. The issue is of particular importance now as the industry strives to increase recovery factors and tap new hydrocarbons to meeting escalating global demand. The task force noted that one of SPE’s goals is to provide the means of transferring technology through the technology life cycle—from inception to maturity—including early in the cycle of “emerging technology.” SPE has been strong in transferring more mature technology through its many publications, conferences, lectures, and workshops. But highlighting “young” technology presents a challenge. Technology that is new in the development cycle often does not lend itself to technical papers, the lifeblood of many SPE events and publications. To that end, the SPE Technical Directors’ Technology Pipeline Task Force aims to accelerate emerging technology through publications and other vehicles. JPT is a natural ally in that goal. JPT is now soliciting information on new and emerging technologies to publish and inform the upstream oil and gas community of their potential. Companies and individuals are invited to submit information on their new technologies for possible publication, both in the JPT print edition and online, by submitting a template that describes the technology and what it can do. The template outlines the minimum content necessary for inclusion. Developers of technology will need to define the reason or need for the technology, its purpose, describe how it works, state its target applications, and note how and where it has been used. In addition, the submission must provide information on any case studies, discuss what would cause the new technology to not work or fail, and describe the possible health, safety, and environmental impact. The technology must provide significant benefits beyond commonly used technologies. It must also be original and, to a certain degree, groundbreaking. Future plans for the technology and whether it has been commercially developed should be given, and a company website and contact information provided. The information should avoid undue commercialism, product cost information, and the use of trademark or other commercial symbols. The technology must be no more than two years old, meaning less than two years since its full commercial deployment or introduction to the marketplace. Companies are not limited to one submission. The sub-missions will be reviewed by SPE’s technical directors for possible inclusion in JPT. In addition to this effort, JPT staff are making a special effort to cover emerging technology and its potential for acceptance in the industry. This month’s issue concludes a three-part series on promising technologies that are vying for wider industry acceptance—managed pressure drilling, seismic while drilling, and permanent downhole monitoring—and other recent articles have covered digital rocks and other promising technologies. If you are interested in submitting information on your new technology or have any questions about this process, please contact me at jdonnelly@spe.org.

QoS Control for Pipelines of Tasks Using Multiple Resources

We consider soft real-time applications organized as pipelines of tasks using resources of different type (communication, computation, and storage). The applications are assumed to be periodically triggered and the different tasks communicate by unidirectional buffers. The problem we cope with is how to effectively share the resources so that some specified Quality of Service (QoS) requirements are met. The QoS considered here is tightly related to the end-to-end temporal behavior of the application. To compensate for time-varying resource requirements, we advocate a distributed control approach whereby the scheduling parameters of each task are tuned depending on the temporal behavior of the application measured by appropriate sensors. The use of real-time scheduling strategies enables a mathematically safe control design in which the QoS requirements are translated into control goals, and formal proofs are provided on the ability of the controller to fulfil these goals. We also offer extensive simulations that validate the approach for multimedia applications.

Multicore Programming Techniques for High-Performance ATE

This paper examined how recent innovations in processor technology are pushing the limits for ATE applications. Various multicore programming techniques were discussed including task parallelism, data parallelism, and pipelining. In addition, an example of optimizing complex analysis was covered. The benefits of adopting multicore technology and parallel software architectures include a reduction in overall test time, more sophisticated simulation approaches, and the ability to analyze complex systems.

81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC

For mobile intelligent robot applications, an 81.6 GOPS object recognition processor is implemented. Based on an analysis of the target application, the chip architecture and hardware features are decided. The proposed processor aims to support both task-level and data-level parallelism. Ten processing elements are integrated for the task-level parallelism and single instruction multiple data (SIMD) instruction is added to exploit the data-level parallelism. The memory-centric network-on-chip (NoC) is proposed to support efficient pipelined task execution using the ten processing elements. It also provides coherence and consistency schemes tailored for 1-to-N and M-to-1 data transactions in a task-level pipeline. For further performance gain, the visual image processing memory is also implemented. The chip is fabricated in a 0.18-mum CMOS technology and computes the key-point localization stage of the SIFT object recognition twice faster than the 2.3 GHz Core 2 Duo processor.

A 201.4 GOPS 496 mW Real-Time Multi-Object Recognition Processor With Bio-Inspired Neural Perception Engine

A 201.4 GOPS real-time multi-object recognition processor is presented with a three-stage pipelined architecture. Visual perception based multi-object recognition algorithm is applied to give multiple attentions to multiple objects in the input image. For human-like multi-object perception, a neural perception engine is proposed with biologically inspired neural networks and fuzzy logic circuits. In the proposed hardware architecture, three recognition tasks (visual perception, descriptor generation, and object decision) are directly mapped to the neural perception engine, 16 SIMD processors including 128 processing elements, and decision processor, respectively, and executed in the pipeline to maximize throughput of the object recognition. For efficient task pipelining, proposed task/power manager balances the execution times of the three stages based on intelligent workload estimations. In addition, a 118.4 GB/s multi-casting network-on-chip is proposed for communication architecture with incorporating overall 21 IP blocks. For low-power object recognition, workload-aware dynamic power management is performed in chip-level. The 49 mm2 chip is fabricated in a 0.13 ?m 8-metal CMOS process and contains 3.7 M gates and 396 KB on-chip SRAM. It achieves 60 frame/sec multi-object recognition up to 10 different objects for VGA (640 × 480) video input while dissipating 496 mW at 1.2 V. The obtained 8.2 mJ/frame energy efficiency is 3.2 times higher than the state-of-the-art recognition processor.

A Pipeline Technique for Dynamic Data Transfer on a Multiprocessor Grid

This paper describes a pipeline technique which is used to redistribute data on a multiprocessor grid during runtime. The main purposes of the algorithm are to minimize the data transfer time, prevent congestion on the ports of the receiving processors, and minimize the number of idle processors. One of the key ideas for this algorithm is the creation of processor classes, firstly introduced by Desprez et al. [IEEE Transactions on Parallel and Distributed Systems 9(2):102 (1998).] Based on the idea of classes, we create the pipeline tasks used to organize the redistribution of data. Our experimental results show that this pipeline technique can significantly reduce the amount of time required to complete a dynamic data transfer task.

On the Optimization of a Pipeline Model to Integrate a Reduced-Dimensionality Schrödinger Equation for Distributed Memory Architectures

This paper examines the problem of dealing with the integration of a two-dimensional Schrödinger equation using a sector-diabatic coupled-channel approach when the coupling matrix is too large to fit into the memory of individual nodes of a multiple-instruction, multiple-data (MIMD) parallel machine. For this case, the distribution of blocks of the coupling matrix among the different nodes and the use of a pipeline model are investigated. To measure performances and to compare them with those measured for a previously optimized task farm model, the pipeline model was implemented on a hypercube and its structure optimized. Benchmarks were performed for dimensions of the coupling matrix manageable by both task farm and pipeline models.

Utilizing the power of high-performance computing

The main focus of this article is the design of embedded signal processing (ESP) application software. We identify the characteristics of such applications in terms of their computational requirements, data layouts, and latency and throughput constraints. We describe an ESP application, an adaptive sonar beamformer. Then, we briefly survey the state-of-the-art in high performance computing (HPC) technology and address the advantages and challenges in using HPC technology for implementing ESP applications. To describe the software design issues in this context, we define a task model to capture the features of ESP applications. This model specifies the independent activities in each processing stage. We also identify various optimization problems in parallelizing ESP applications. We address the key issues in developing scalable and portable algorithms for ESP applications. We focus on the algorithmic issues in exploiting coarse-grain parallelism. These issues include data layout design and task mapping. We show a task mapping methodology for application software development based on our execution model (Lee et al., 1998). This uses a novel stage partitioning technique to exploit the independent activities in a processing stage. We use our methodology to maximize the throughput of an ESP application for a given platform size. The resulting application software using this methodology is called a software task pipeline. An adaptive sonar beamformer has been implemented using this design methodology.

Optimal mapping of sequences of data parallel tasks

Many applications in a variety of domains including digital signal processing, image processing and computer vision are composed of a sequence of tasks that act on a stream of input data sets in a pipelined manner. Recent research has established that these applications are best mapped to a massively parallel machine by dividing the tasks into modules and assigning a subset of the available processors to each module. This paper addresses the problem of optimally mapping such applications onto a massively parallel machine. We formulate the problem of optimizing throughput in task pipelines and present two new solution algorithms. The formulation uses a general and realistic model for inter-task communication, takes memory constraints into account, and addresses the entire problem of mapping which includes clustering tasks into modules, assignment of processors to modules, and possible replication of modules. The first algorithm is based on dynamic programming and finds the optimal mapping of k tasks onto P processors in O(P 4 k 2 ) time. We also present a heuristic algorithm that is linear in the number of processors and establish with theoretical and practical results that the solutions obtained are optimal in practical situations. The entire framework is implemented as an automatic mapping tool for the Fx parallelizing compiler for High Performance Fortran. We present experimental results that demonstrate the importance of choosing a good mapping and show that the methods presented yield efficient mappings and predict optimal performance accurately.

Thrifty execution of task pipelines

A sequence of tasks that must be performed on a sequential database can be scheduled in various ways. Schedules will differ with respect to the number of accesses made to peripheral storage devices and the amount of memory space consumed by buffers. Buffer requirements are discussed for task schedules that avoid accesses to peripherals storing the sequential database. The relationship between certain thrifty scheduling policies and loop jamming, a standard code optimization technique, is also identified. Application to UNIX pipelines and to file processing is discussed.