Target Hardware Research Articles

Self-Organizing Maps for Clustering Hyperspectral Images On-Board a CubeSat

Hyperspectral remote sensing reveals detailed information about the optical response of a scene. Self-Organizing Maps (SOMs) can partition a hyperspectral dataset into clusters, both to enable more analysis on-board the imaging platform and to reduce downlink time. Here, the expected on-board performance of the SOM algorithm is calculated within two different satellite operational procedures: one in which the SOM is trained prior to imaging, and another in which the training is part of the operations. The two procedures are found to have advantages that are suitable to quite different situations. The computational requirements for SOMs of different sizes are benchmarked on the target hardware for the HYPSO-1 mission, and dimensionality reduction (DR) is tested as a way of reducing the SOM network size. We find that SOMs can run on the target on-board processing hardware, can be trained reasonably well using less than 0.1% of the total pixels in a scene, are accelerated by DR, and can achieve a relative quantization error of about 1% on scenes acquired by a previous hyperspectral imaging satellite, HICO. Moreover, if class labels are assigned to the nodes of the SOM, these networks can classify with a comparable accuracy to support vector machines, a common benchmark, on a few simple scenes.

Using Ginkgo's memory accessor for improving the accuracy of memory‐bound low precision BLAS

AbstractThe roofline model not only provides a powerful tool to relate an application's performance with the specific constraints imposed by the target hardware but also offers a graphic representation of the balance between memory access cost and compute throughput. In this work, we present a strategy to break up the tight coupling between the precision format used for arithmetic operations and the storage format employed for memory operations. (At a high level, this idea is equivalent to compressing/decompressing the data in registers before/after invoking store/load memory operations.) In practice, we demonstrate that a “memory accessor” that hides the data compression behind the memory access, can virtually push the bandwidth‐induced roofline, yielding higher performance for memory‐bound applications using high precision arithmetic that can handle the numerical effects associated with lossy compression. We also demonstrate that memory‐bound applications operating on low precision data can increase the accuracy by relying on the memory accessor to perform all arithmetic operations in high precision. In particular, we demonstrate that memory‐bound BLAS operations (including the sparse matrix‐vector product) can be re‐engineered with the memory accessor and that the resulting accessor‐enabled BLAS routines achieve lower rounding errors while delivering the same performance as the fast low precision BLAS.

FLASH: F ast Neura l A rchitecture S earch with H ardware Optimization

Neural architecture search (NAS) is a promising technique to design efficient and high-performance deep neural networks (DNNs). As the performance requirements of ML applications grow continuously, the hardware accelerators start playing a central role in DNN design. This trend makes NAS even more complicated and time-consuming for most real applications. This paper proposes FLASH, a very fast NAS methodology that co-optimizes the DNN accuracy and performance on a real hardware platform. As the main theoretical contribution, we first propose the NN-Degree, an analytical metric to quantify the topological characteristics of DNNs with skip connections (e.g., DenseNets, ResNets, Wide-ResNets, and MobileNets). The newly proposed NN-Degree allows us to do training-free NAS within one second and build an accuracy predictor by training as few as 25 samples out of a vast search space with more than 63 billion configurations. Second, by performing inference on the target hardware, we fine-tune and validate our analytical models to estimate the latency, area, and energy consumption of various DNN architectures while executing standard ML datasets. Third, we construct a hierarchical algorithm based on simplicial homology global optimization (SHGO) to optimize the model-architecture co-design process, while considering the area, latency, and energy consumption of the target hardware. We demonstrate that, compared to the state-of-the-art NAS approaches, our proposed hierarchical SHGO-based algorithm enables more than four orders of magnitude speedup (specifically, the execution time of the proposed algorithm is about 0.1 seconds). Finally, our experimental evaluations show that FLASH is easily transferable to different hardware architectures, thus enabling us to do NAS on a Raspberry Pi-3B processor in less than 3 seconds.

HW-FlowQ: A Multi-Abstraction Level HW-CNN Co-design Quantization Methodology

Model compression through quantization is commonly applied to convolutional neural networks (CNNs) deployed on compute and memory-constrained embedded platforms. Different layers of the CNN can have varying degrees of numerical precision for both weights and activations, resulting in a large search space. Together with the hardware (HW) design space, the challenge of finding the globally optimal HW-CNN combination for a given application becomes daunting. To this end, we propose HW-FlowQ, a systematic approach that enables the co-design of the target hardware platform and the compressed CNN model through quantization. The search space is viewed at three levels of abstraction, allowing for an iterative approach for narrowing down the solution space before reaching a high-fidelity CNN hardware modeling tool, capable of capturing the effects of mixed-precision quantization strategies on different hardware architectures (processing unit counts, memory levels, cost models, dataflows) and two types of computation engines (bit-parallel vectorized, bit-serial). To combine both worlds, a multi-objective non-dominated sorting genetic algorithm (NSGA-II) is leveraged to establish a Pareto-optimal set of quantization strategies for the target HW-metrics at each abstraction level. HW-FlowQ detects optima in a discrete search space and maximizes the task-related accuracy of the underlying CNN while minimizing hardware-related costs. The Pareto-front approach keeps the design space open to a range of non-dominated solutions before refining the design to a more detailed level of abstraction. With equivalent prediction accuracy, we improve the energy and latency by 20% and 45% respectively for ResNet56 compared to existing mixed-precision search methods.

Towards performance portability in the Spark astrophysical magnetohydrodynamics solver in the Flash-X simulation framework

Simulations of core-collapse supernovae, and other astrophysical phenomena, are quintessential extreme-scale computing challenges. For core-collapse supernova simulations to be carried out by the ExaStar project under the Exascale Computing Project umbrella, a robust, efficient, and state-of-the-art magnetohydrodynamics solver is a critical requirement. In Flash-X, the primary software instrument for ExaStar, a new magnetohydrodynamics solver has been designed and implemented from the ground up to achieve accuracy and efficiency for simulations of complex astrophysical flows. This new solver, dubbed Spark, uses high-order spatial reconstruction, Runge–Kutta time integration, and an efficient cell-centered approach to satisfying the divergence-free condition for the magnetic fields. Spark was written to be optimized for data locality in cache hierarchy of CPUs. Since data locality optimizations for cache hierarchy are not directly compatible with those of accelerators, we have taken the approach of using program synthesis to avoid massive amounts of code replication that would be necessary if we were to maintain two different versions of the solver. Our program synthesis relies on a simple key-dictionary approach, implemented in python, that enables us to assemble the version of the solver suitable for the target hardware from code fragments identified by specific keys. In this paper, we describe the data locality optimizations of the solver for CPUs and accelerators and the program synthesis tools that enable this portability. We also detail the parallel performance of Spark for both CPUs and accelerators.

Interpreted synchronous extension of time Petri nets

Our work is integrated into a global methodology to design synchronously executed embedded critical systems. It is used for the development of medical devices implanted into human body to perform functional electrical stimulation solutions (used in pacemakers, deep brain stimulation...). These systems are of course critical and real time, and the reliability of their behaviors must be guaranteed. These medical devices are implemented into a programmable logic circuit in a synchronous way, which allows efficient implementation (space, consumption and actual parallelism of tasks execution). This paper presents a solution that helps to prove that the behavior of the implemented system respects a set of properties, using Petri nets for modeling and analysis purposes. But one problem in formal methods is that the hardware target and the implementation strategy can have an influence on the execution of the system, but is usually not considered in the modeling and verification processes. Resolving this issue is the goal of this article. Our work has two main results: an operational one, and a theoretical one. First, we can now design critical controllers with hard safety or real time constraints, being sure the behavior is still guaranteed during the execution. Second, this work broadens the scope of expressivity and analyzability of Petri nets extensions. Until then, none managed in the same formalism, both for modeling and analysis, all the characteristics we have considered (weights on arcs, specific test and inhibitor arcs, interpretation, and time intervals, including the management of effective conflicts and the blocking of transitions).

DSP-FPGA based real time implementation of carrier based PWM technique for an indirect matrix converter

ABSTRACT The main focus of the presented work is to provide an easy, efficient and rapid method of implementing the carrier-based PWM (CPWM) technique for the three-to-three phase indirect matrix converter (IMC). The control platforms DSP (TMS320F28335) and the FPGA (Spartan-6) are used for realising the CPWM scheme for the IMC. In the presented work, the auto code generation facility provided by the simcoder module of the PSIM software is utilised to develop the C-code for the TI F28335 hardware target. The FPGA is used to perform the logical operations on the switching pulses produced by the DSP. The complete procedure of implementing the CPWM scheme in DSP using simcoder module of PSIM and FPGA is demonstrated in this work. The simulation and the experimental results are included to verify the effective implementation of the CPWM scheme for the IMC.

NOP-DH – Evaluation Over Bitonic Sort Algorithm

The growing use of Field Programmable Gate Array (FPGA) to increase application performance requires tools that simplify the digital circuit development process. Traditional approaches of Hardware Description Languages (HDLs) are complex and require specialized knowledge at a low-level abstraction. In turn, different approaches called High-Level Synthesis (HLS) aim at facilitating the development of FPGA applications, making this development process closer to those of software using programming languages such as C or C++. However, these alternatives do not properly exploit the parallelism capability of FPGAs as they are based on usual sequential approaches and, moreover, continue to depend on developer technical knowledge about the target hardware. The Notification Oriented Paradigm (NOP) emerges as an alternative to develop and execute applications. The NOP brings a new inference concept based on precise notifying collaborative entities. This type of inference allows presenting an innovative way of implicitly achieving decoupled and decentralized solutions, thereby enabling parallelism and distribution in a level of granularity as fine as possible in the envisaged computational platform. In this context, researches on NOP have proposed the design of digital circuits based on the NOP model, called NOP Digital Hardware (DH). In this paper, it is proposed to evaluate the use of the NOP-DH to develop the well-known Bitonic Sort, which is a sort algorithm useful as benchmark. This algorithm has particular properties that are advantageous for parallel execution, especially in FPGAs. Experiments were performed to compare the performance, amount of logic elements, and maximum frequency of NOP-DH against the traditional VHDL approach. These experiments demonstrated that even with a higher abstraction level of development, NOP-DH circuits achieve similar results when compared to the traditional development in VHDL.

Power Electronics and Drives: Simulation to Implementation in Minutes: A Novel Implementation Tool for Power Engineers

Power electronics and drives play a crucial role in various industrial applications, and therefore its control systems have become more significant since the turn of this century in the developing world. A power engineer must first control the system, design and simulate its model, and then implement it to verify the simulation results. Lucas Nulle Servo Drive (LNSD) system is a powerful tool for power engineers, researchers, professors, and students to enhance research efficiency. The system comprises self-commuted converter circuits with insulated-gate bipolar transistors (IGBTs), which incorporate control and measurement of power electronics parameters. The operation and recording of measurements can be done using virtual instruments. On the other hand, the system can operate without a computer. It can also be expanded through a MATLAB interface that allows to upload MATLAB projects onto a power electronics system and test them out using real hardware components in minutes. The steps involved in the project are first creating a model using LN MATLAB Toolbox, simulation of the model, generating code for target hardware, and measurement of data using LN scope. The results can then compare with those obtained in the simulation. This article briefly introduces the LNSD system and the two research studies: automatic control and novel model predictive control (NMPC) of variable speed fault-tolerant synchronous servo motor drive using MATLAB/Simulink.

A Taxonomy of Modern GPGPU Programming Methods: On the Benefits of a Unified Specification

Several Application Programming Interfaces (APIs) and frameworks have been proposed to simplify the development of General-Purpose GPU (GPGPU) applications. GPGPU application development typically involves specific customization for the target operating systems and hardware devices. The effort to port applications from one API to the other (or to develop multi-target applications) is complicated by the availability of a plethora of specifications, which in essence offers very similar underlying functionality. In this work we provide an in-depth study of six state-of-the-art GPGPU APIs. From these we derive a taxonomy of the common semantics and propose a unified specification. We describe a methodology to translate this unified specification into different target APIs. This simplifies cross-platform application development and provides a clean framework for benchmarking. Our proposed unified specification is called GUST (GPGPU Unified Specification and Translation) and it captures common functionality found in compute-only APIs (e.g., CUDA and OpenCL), in the compute pipeline of traditional graphic-oriented APIs (e.g., OpenGL and Direct3D11) and in last-generation bare-metal APIs (e.g., Vulkan and Direct3D12). The proposed translation methodology solves differences between specific APIs in a transparent manner, without hiding available tuning knobs for compute kernel optimizations and fostering best programming practices in a simple manner.

Development of a hardware-in-the-loop demonstrator for the validation of fault-tolerant control methods for a hybrid UAV

Many aircraft are inherently over-actuated with regard to their input variables. This can be particularly advantageous in the context of unmanned aerial vehicles (UAV), where actuator functions can fail in critical situations. In such cases, the redundant actuators can be used to further fulfil the control strategies used and thus increase the operational safety. Within such an active fault-tolerant control system, a fault detection and isolation (FDI) module is required. To evaluate such safety–critical systems, hardware-in-the-loop simulations (HIL) are a necessary step prior to real flight tests. These simulations can verify the correct implementation of the flight controller on the target hardware as well as the real-time capability of the algorithms used. Particularly in the context of active fault-tolerant control, investigations concerning the robustness of the used FDI module with regard to real, noisy sensor signals, which can be generated by a HIL demonstrator, are of utter importance. This paper presents the development of a HIL demonstrator for the validation of fault-tolerant control methods for a hybrid UAV. This includes a detailed description of the demonstrator’s design, control and interfacing between the integrated subsystems. As an application example, a hybrid UAV model will be shortly presented, which, in addition to the primary aerodynamic control surfaces, can also use four lift rotors to control the aircraft during cruise and is therefore inherently over-actuated. Finally, a closed-loop real-time simulation of the UAV model on the HIL demonstrator is presented on the basis of the exemplary simulation of an actuator failure and subsequent reconfiguration by the fault-tolerant flight control law.

Machine Learning–enabled Scalable Performance Prediction of Scientific Codes

Hardware architectures become increasingly complex as the compute capabilities grow to exascale. We present the Analytical Memory Model with Pipelines (AMMP) of the Performance Prediction Toolkit (PPT). PPT-AMMP takes high-level source code and hardware architecture parameters as input and predicts runtime of that code on the target hardware platform, which is defined in the input parameters. PPT-AMMP transforms the code to an (architecture-independent) intermediate representation, then (i) analyzes the basic block structure of the code, (ii) processes architecture-independent virtual memory access patterns that it uses to build memory reuse distance distribution models for each basic block, and (iii) runs detailed basic-block level simulations to determine hardware pipeline usage. PPT-AMMP uses machine learning and regression techniques to build the prediction models based on small instances of the input code, then integrates into a higher-order discrete-event simulation model of PPT running on Simian PDES engine. We validate PPT-AMMP on four standard computational physics benchmarks and present a use case of hardware parameter sensitivity analysis to identify bottleneck hardware resources on different code inputs. We further extend PPT-AMMP to predict the performance of a scientific application code, namely, the radiation transport mini-app SNAP. To this end, we analyze multi-variate regression models that accurately predict the reuse profiles and the basic block counts. We validate predicted SNAP runtimes against actual measured times.

Learning based compilation of embedded applications targeting minimal energy consumption

Abstract The choice of correct optimization passes during compilation is one of the major factors that determines the performance and energy consumption of an application when executed on a target hardware. However, making such a choice is challenging since it requires knowledge of target architecture, code features and compiler pass interdependence. Software developers mostly rely on heuristic approaches while choosing the optimization passes. However, such heuristic solutions and random choices often yield sub-optimal results. In this work, we propose an automated technique of determining the optimal compiler optimization setting for minimum energy consumption utilizing power profile results and performance characteristics from real hardware and machine learning models. The proposed approach on one hand brings about reduction in energy consumption and on the other releases embedded software developers from making the complicated compiler optimization choices for each application. Our proposed five phase strategy when implemented on multi-core ARM based ODROID-XU4 experimental platform using the Clang Compiler shows a maximum of 8.43% improvement in power dissipation and a maximum of 27.27% in energy consumption for MiBench and Polybench representative benchmarks in comparison to state-of-art energy aware compilation strategies.

Simulator for Interactive and Effective Organization of Things in Edge Cluster Computing.

Edge computing is intended to process events that occur at the endpoint of the Internet of Things (IoT) network quickly and intelligently. Edge regions must be organized effectively to facilitate cooperation so that the intention of edge computing can be realized. However, inevitably, many human and material resources are required in the process of arranging things in the edge area to confirm the appropriateness of the thing operation. To address this problem, we proposed a simulator that created a virtual space for edge computing and provided an interactive role and effective organization for edge things. The proposed simulator was aimed at Raspberry Pi as the physical hardware target. To prove the accuracy of the proposed simulator, the similarity between the proposed simulator and the physical target Raspberry Pi was evaluated based on three metrics while executing several applications. In the experiment, several edge-computing service applications were performed in various cluster architecture types formed by the proposed simulator. To support effective resource usage and fast real-time response for edge computing, the proposed simulator identified a suitable number of things in forming the edge cluster.

Improved Sc-44 production in a siphon-style liquid target on a medical cyclotron

In order to use new and promising radiometals for molecular imaging, it is important that they can be obtained as inexpensively and easily as possible. This often requires a cyclotron with solid target hardware or a radionuclide generator, which are not widely available for rarely used radionuclides. Here, we investigate the improved production of 44Sc with a siphon-style liquid target system and compare to our previous work with a simple liquid target. A metal salt solution with a high concentration of natural abundance Ca(NO3)2 (0.14 g/cm3) was irradiated with a medical cyclotron (12 MeV protons; 20 μA). 44Sc was produced via the natCa(p,x)44Sc reaction. As the pressure increase during irradiation was reduced in the siphon-style target, it was possible to irradiate with a higher proton beam current (20 μA) than with the simple liquid target system (7.9 μA). In addition, the saturation yield per μA of 44Sc was increased by a factor of 3.18 ± 0.05 (6.2 ± 0.1 MBq/μA with the siphon target versus 1.94 ± 0.08 MBq/μA with the simple target). This results in an overall increase in 44Sc activity by a factor of 11.

Accelerating Deep Neural Networks implementation: A survey

Recently, Deep Learning (DL) applications are getting more and more involved in different fields. Deploying such Deep Neural Networks (DNN) on embedded devices is still a challenging task considering the massive requirement of computation and storage. Given that the number of operations and parameters increases with the complexity of the model architecture, the performance will strongly depend on the hardware target resources and basically the memory footprint of the accelerator. Recent research studies have discussed the benefit of implementing some complex DL applications based on different models and platforms. However, it is necessary to guarantee the best performance when designing hardware accelerators for DL applications to run at full speed, despite the constraints of low power, high accuracy and throughput. Field Programmable Gate Arrays (FPGAs) are promising platforms for the deployment of large-scale DNN which seek to reach a balance between the above objectives. Besides, the growing complexity of DL models has made researches think about applying optimization techniques to make them more hardware-friendly. Herein, DL concept is presented. Then, a detailed description of different optimization techniques used in recent research works is explored. Finally, a survey of research works aiming to accelerate the implementation of DNN models on FPGAs is provided.

OpenVINO Deep Learning Workbench: Towards Analytical Platform for Neural Networks Inference Optimization

Modern neural network methods make it possible to obtain qualitative results that open the colossal potential for integrating them into industrial applications. Therefore, there is a need for systems like the OpenVINO Deep Learning Workbench to analyze and optimize neural networks’ performance on target devices. As the primary tool for inference, the OpenVINO open environment is used, which provides a wide variety of options to speed up network execution on the target hardware.

ANNETTE: Accurate Neural Network Execution Time Estimation With Stacked Models

With new accelerator hardware for DNN, the computing power for AI applications has increased rapidly. However, as DNN algorithms become more complex and optimized for specific applications, latency requirements remain challenging, and it is critical to find the optimal points in the design space. To decouple the architectural search from the target hardware, we propose a time estimation framework that allows for modeling the inference latency of DNNs on hardware accelerators based on mapping and layer-wise estimation models. The proposed methodology extracts a set of models from micro-kernel and multi-layer benchmarks and generates a stacked model for mapping and network execution time estimation. We compare estimation accuracy and fidelity of the generated mixed models, statistical models with the roofline model, and a refined roofline model for evaluation. We test the mixed models on the ZCU102 SoC board with DNNDK and Intel Neural Compute Stick 2 on a set of 12 state-of-the-art neural networks. It shows an average estimation error of 3.47% for the DNNDK and 7.44% for the NCS2, outperforming the statistical and analytical layer models for almost all selected networks. For a randomly selected subset of 34 networks of the NASBench dataset, the mixed model reaches fidelity of 0.988 in Spearman's rank correlation coefficient metric. The code of ANNETTE is publicly available at https://github.com/embedded-machine-learning/annette.

IMPROVING THE EFFICIENCY OF THE AUTOMATED SYSTEM OF CONTROL FOR OIL TRANSPORTATION PROCESS ON THE BASIS OF INTELLECTUAL TECHNOLOGIES

The paper considers an urgent scientific and practical task, which consists in the development of new ones. An urgent scientific and practical task is investigated, which consists in the development of new methods and methods for assessing the technical condition of oil trunk pipelines, which will provide safe automated control of the oil transportation system. It has been determined that in conditions of intensive aging of fixed assets of oil transportation systems and financial constraints, complex technical diagnostics of oil trunk pipelines becomes the most effective means of ensuring the reliability and safety of the entire oil transportation system.
 Simulation modeling is inherently complex and time-consuming process that requires many computations, including distributed ones. There are several stages of simulation modeling (MI). In the most general, enlarged form, these are the following stages: setting the problem, collecting and processing data, developing and adjusting the model, modeling, accumulating results, planning experiments, analyzing the results, documenting and storing the results. To carry out such research, various systems for the automation of imitation research (SAIS) are being created. A cloud-based approach to conducting MI, which makes it possible to simplify and unify research for the end user, to abstract the researcher from the technical features of the organization of calculations. Cloud AISI is invariant with respect to the target hardware and software. That is why the development of new and promising control and management tools based on artificial intelligence with a combination of cloud technologies is an urgent scientific and practical task, based on the results of which the main scientific problems requiring further research have been identified.

Knowledge-Based Verification of Concatenative Programming Patterns Inspired by Natural Language for Resource-Constrained Embedded Devices.

We propose a methodology to verify applications developed following programming patterns inspired by natural language that interact with physical environments and run on resource-constrained interconnected devices. Natural language patterns allow for the reduction of intermediate abstraction layers to map physical domain concepts into executable code avoiding the recourse to ontologies, which would need to be shared, kept up to date, and synchronized across a set of devices. Moreover, the computational paradigm we use for effective distributed execution of symbolic code on resource-constrained devices encourages the adoption of such patterns. The methodology is supported by a rule-based system that permits runtime verification of Software Under Test (SUT) on board the target devices through automated oracle and test case generation. Moreover, verification extends from syntactic and semantic checks to the evaluation of the effects of SUT execution on target hardware. Additionally, by exploiting rules tying sensors and actuators to physical quantities, the effects of code execution on the physical environment can be verified. The system is also able to build test code to highlight software issues that may arise during repeated SUT execution on the target hardware.