Target Field Programmable Gate Array Research Articles

SHA-256 Hardware Proposal for IoT Devices in the Blockchain Context.

This work proposes an implementation of the SHA-256, the most common blockchain hash algorithm, on a field-programmable gate array (FPGA) to improve processing capacity and power saving in Internet of Things (IoT) devices to solve security and privacy issues. This implementation presents a different approach than other papers in the literature, using clustered cores executing the SHA-256 algorithm in parallel. Details about the proposed architecture and an analysis of the resources used by the FPGA are presented. The implementation achieved a throughput of approximately 1.4 Gbps for 16 cores on a single FPGA. Furthermore, it saved dynamic power, using almost 1000 times less compared to previous works in the literature, making this proposal suitable for practical problems for IoT devices in blockchain environments. The target FPGA used was the Xilinx Virtex 6 xc6vlx240t-1ff1156.

Improving the exploitability of Simulated Adiabatic Bifurcation through a flexible and open-source digital architecture

Combinatorial Optimization (CO) problems exhibit exponential complexity, constraining classical computers from providing fast and satisfactory outcomes. Quantum Computers (QCs) can effectively find optimal or near-optimal solutions by exploring the solutions space of a problem encoded in a qubits system, exploiting principles of quantum mechanics. However, non-idealities and high costs limit their availability. These can be overcome by emulating QCs on cheaper and more accessible classical computing platforms, like Field-Programmable Gate Arrays (FPGAs). This article presents a digital architecture, implementing the Ising-compatible Simulated Adiabatic Bifurcation algorithm. It mimics the quantum adiabatic evolution of a network of non-linear Kerr oscillators. The architecture, described in VHDL and targeting FPGAs, consists of processing elements for computing the Kerr oscillators’ evolution, a set of units considering their Ising-related interactions and an evolution variables update unit. The proposed approach includes a speedup-targeting approximation of the algorithm, a method for handling single-variable constraints, and a software model that allows architecture customization for specific problems. Tests were conducted using an Altera Cyclone V SoC with FPGA logic and the Nios II processor for interface purposes. The results demonstrate the functionality of the architecture and its scalability with the problem size, making it suitable for real-world applications.

Optimizing Neural Network Inference in Edge Robotics by Harnessing FPGA Hardware Acceleration

This research explores advancements in neural network inference for edge robotics through the implementation of hardware acceleration using Field-Programmable Gate Arrays (FPGA). Leveraging FPGA's versatility in custom hardware design, the research optimizes performance and energy efficiency by utilizing features such as Digital Signal Processors (DSP), Multiply-Accumulate (MAC) arrays, parallel processing units, Convolutional Neural Networks (CNN), and custom accelerators. The computational power of FPGA-based architectures is harnessed to significantly enhance the speed and efficiency of neural network inference tasks in edge robotics applications. Key aspects include the utilization of DSP blocks for efficient signal processing, MAC arrays for high-speed matrix operations crucial in neural network computations, and parallel processing units for concurrent execution of multiple tasks, improving overall system throughput. The integration of CNN directly onto FPGA hardware allows for minimal-latency inference, making it ideal for real-time applications in edge robotics scenarios. Custom accelerators tailored to specific neural network operations further optimize performance and resource utilization. The research involves the meticulous design and synthesis of hardware modules tailored to the target FPGA platform. Through rigorous optimization and parallelization techniques, the goal is to maximize resource utilization while minimizing latency and power consumption. The experimental findings showcase remarkable results, including a substantial increase in throughput, with values reaching up to 150 images/sec, and impressive accuracy rates exceeding 95% in classification tasks.

Remote field-programmable gate array laboratory for signal acquisition and design verification

A remote laboratory utilizing field-programmable gate array (FPGA) technologies enhances students’ learning experience anywhere and anytime in embedded system design. Existing remote laboratories prioritize hardware access and visual feedback for observing board behavior after programming, neglecting comprehensive debugging tools to resolve errors that require internal signal acquisition. This paper proposes a novel remote embedded-system design approach targeting FPGA technologies that are fully interactive via a web-based platform. Our solution provides FPGA board access and debugging capabilities beyond the visual feedback provided by existing remote laboratories. We implemented a lab module that allows users to seamlessly incorporate into their FPGA design. The module minimizes hardware resource utilization while enabling the acquisition of a large number of data samples from the signal during the experiments by adaptively compressing the signal prior to data transmission. The results demonstrate an average compression ratio of 2.90 across three benchmark signals, indicating efficient signal acquisition and effective debugging and analysis. This method allows users to acquire more data samples than conventional methods. The proposed lab allows students to remotely test and debug their designs, bridging the gap between theory and practice in embedded system design.

Design of pseudorandom number generator based on a controllable multi-double-scroll chaotic system

The generation, implementation, and application of multi-scroll chaotic systems have been extensively studied due to their complex dynamic behaviors. This paper introduces a new controlled multi-double-scroll chaotic system and its corresponding implementation on a digital platform, the Field Programmable Gate Array (FPGA). The proposed system can generate 2N+1 and 2N+2 numbers of double-scroll attractors. In particular, the system has controllable multistability and multi-double-scroll complete amplitude control characteristics. The numerical analyses of Lyapunov exponents, bifurcation diagrams, phase diagrams, and basin of attraction show that the system exhibits complex dynamic behaviors. Furthermore, a new pseudo-random number generator (PRNG) is designed based on the multi-double-scroll chaotic system (MDSCS), in which a post-processing circuit is used to improve the quality of the generator. The PRNG has a high data throughput and uses only a small amount of resources in the target FPGA. The proposed PRNG uses less than 1% of the resources of the target FPGA and delivers a data bit throughput of 7.2 Gbps/s. To our best knowledge, it reaches the highest data throughput of PRNG based on continuous chaotic systems. The evaluation sequences are tested using generic randomness tests such as NIST SP800-22, TestU01, and Histograms. The experimental results show that the random sequences generated by our design have passed all the test items, which means that they will have excellent performance in the application.

High-level synthesis assisted, low-latency, area- and power-optimized FPGA implementation of MUSIC algorithm for direction-of-arrival estimation

For multiple signal-processing applications, estimating the target’s speed, distance, and elevation angle by using applications running in real time and consequently, fast data rates is important. Custom hardwares, such as field programmable gate arrays (FPGAs), are often used to prototype and deploy such signal-processing algorithms. Multiple signal classification (MUSIC) is typically used for direction-of-arrival (DOA) estimation. It involves complex mathematical operations such as covariance matrix computation, eigen value decomposition, and peak value search for signal values. With a novel high-level synthesis (HLS)-based design approach that optimizes the bit widths for the eigen value decomposition logic, this study presents an area and speed-optimal implementation of MUSIC algorithm on FPGA. The final implementation involving the covariance matrix computation, eigen value decomposition, and peak search was implemented on Xilinx Zynq (XC7Z020) FPGA. Because of its optimum bit widths, area utilization was minimized and operation frequency on the target FPGA was maximized. The proposed design works in real time to estimate the DOA in less than 1.7 µs (15 % faster than reported values) and uses up to 30 % less resources on the target FPGA compared with other reported implementations.

Machine Learning Based Framework for Fast Resource Estimation of RTL Designs Targeting FPGAs

Field-programmable gate arrays (FPGAs) have grown to be an important platform for integrated circuit design and hardware emulation. However, with the dramatic increase in design scale, it has become a key challenge to partition very large scale integration into multi-FPGA systems. Fast estimation of FPGA on-chip resource usage for individual sub-circuit blocks early in the circuit design flow will provide an essential basis for reasonable circuit partition. It will also help FPGA designers to tune the circuits in hardware description language. In this article, we propose a framework for fast estimation of the on-chip resources consumed by register transfer level (RTL) designs with machine learning methods. We extensively collect RTL designs as a dataset, extract features from the result of a parser tool and analyze their roles, and train a targeted three-stage ensemble learning model. A 5,513× speedup is achieved while having 27% relative absolute error. Although the effect is sufficient to support RTL circuit partition, we discuss how the estimation quality continues to be improved.

FPGA-Based Statechart Controller for MPPT of a Photovoltaic System

Conventional Maximum Power Point Tracking (MPPT) controllers in photovoltaic (PV) systems are seen to achieve tracking speeds in range of milliseconds. Power-electronic circuits in these systems many-a-time demand faster control actions in microseconds, as they operate at high frequencies, and also, a delay in control action would lead to a corresponding power-loss. Hence, an MPPT controller delivering such fast tracking speeds would improve overall system performance. In this work, an Field Programmable Gate Array (FPGA) based Statechart Controller is developed to perform MPPT control of the PV system. The developed Statechart Controller is tested using software-in-the-loop simulation(SILS) and results are presented. With inputs from a programmable logic controller emulating PV characteristic curves, the Statechart Controller is then deployed in a target FPGA. A comparison between performance with conventional MPPT controller and Statechart Controller is presented and results indicate that the latter is more effective in terms of tracking speeds, determinism, and modularity.

Unsupervised recycled FPGA detection using exhaustive nearest neighbor residual analysis

Measuring and analyzing aging-induced delay degradation of ring oscillators (ROs) is an effective method to detect recycled field-programmable gate arrays (FPGAs). However, detection methods of conventional recycled FPGAs detection methods assume the existence of known fresh FPGAs (KFFs) as training data for machine-learning-based classification, which is an unrealistic assumption. In this paper, we propose an unsupervised recycled FPGA detection method, where little information on KFF is available. In the proposed method, estimated frequency is calculated from neighboring ROs, and then the residual frequency between the measured and estimated frequencies is used for the detection. Because of the systematic component of process variation, the frequencies of neighboring ROs should be similar when the target FPGA is fresh. Therefore, if the residual is high, the target FPGA is determined as recycled. Experiments using 25 commercial FPGAs under various aging scenarios demonstrate that the proposed method successfully distinguishes between recycled and fresh FPGAs.

Efficient Hardware Optimization for CNN

Convolutional Neural Networks (CNN) architectures have been increasingly well-known for image processing applications such as object detection, and remote sensing. Some applications like these systems need to adopt CNN methods for real-time implementation. Embedded devices like Field Programmable Gate Arrays (FPGA) technologies are a favorable alternative to implementing CNN-based algorithms. However, FPGA has some drawbacks such as limited resources and bottlenecks, it is difficult and so crucial to map the whole CNN that has a high number of layers, on FPGA without any optimization. Therefore, hardware optimization techniques are compulsory. In this study, an FPGA-based CNN architecture using high-level synthesis (HLS) is demonstrated, and a synthesis report is created for Xilinx Zynq-7000 xc7z020-clg484-1 target FPGAs. By implementing the CNN architecture on an FPGA platform, the implemented architecture has been fastened. To improve the throughput, the proposed design is optimized for convolutional layers. The most important contribution of this study is to perform optimization on the convolution layer by unrolling kernels and input feature maps and examine the effects on throughput, latency, and hardware resources. In this study, throughput is 15.6 GOP/s for the first convolution layer. With the proposed method in the study, approximately x2.6 acceleration in terms of latency and throughput was achieved compared to the baseline design.

Hardware Implementation of a Fixed-Point Decoder for Low-Density Lattice Codes

This paper describes a field-programmable gate array (FPGA) implementation of a fixed-point low-density lattice code (LDLC) decoder where the Gaussian mixture messages that are exchanged during the iterative decoding process are approximated to a single Gaussian. A detailed quantization study is first performed to find the minimum number of bits required for the fixed-point decoder to attain a frame error rate (FER) performance similar to floating-point. Then efficient numerical methods are devised to approximate the required non-linear functions. Finally, the paper presents a comparison of the performance of the different decoder architectures as well as a detailed analysis of the resource requirements and throughput trade-offs of the primary design blocks for the different architectures. A novel pipelined LDLC decoder architecture is proposed where resource re-utilization along with pipelining allows for a parallelism equivalent to 50 variable nodes on the target FPGA device. The pipelined architecture attains a throughput of 10.5 Msymbols/sec at a distance of 5 dB from capacity which is a 1.8times improvement in throughput compared to an implementation with 20 parallel variable nodes without pipelining. This implementation also achieves 24times improvement in throughput over a baseline serial decoder.

FPGA Hardware in the Loop Validation of Asynchronous Machine with Full Direct Torque Control Implementation

This article provides a full hardware implementation for direct torque control (DTC) of an asynchronous motor (AM) on the Field Programmable Gate Array (FPGA). Due to its high processing frequency, the FPGA circuit presents an alternative for achieving a high performance DTC implementation. This cannot be achieved by any DSP or microcontroller application. The proposed hardware architecture implements three components of DTC control strategy (the integral proportional speed regulator, the estimation and the switching blocks). This implementation has the advantage of being faster, more efficient and with minimum hardware resources on the target FPGA board. The hardware architecture of the DTC control was designed and simulated in Matlab / Simulink using XSG blocks, then synthesized with the Xilinx ISE 14.2 tool, implemented and validated on the Xilinx Virtex-4 FPGA circuit by Hardware in the Loop process.

Reconfigurable content-addressable memory (CAM) on FPGAs: A tutorial and survey

Content-addressable memory (CAM) is a massively parallel searching device that returns the address of a given search input in one clock cycle. Field-programmable gate array (FPGA)-based CAMs are becoming popular due to their applications in the latest networking systems, e.g., software-defined networks (SDNs) leading to upcoming 5G networks. Ternary CAM (TCAM) implements a routing table in a network router to classify and forward data packets where don’t care bits (X-bits) correspond to multiple addresses. FPGAs do not have a hard-core CAM, although it is a prime element in networking applications. This paper serves as a comprehensive survey on FPGA-based CAM/TCAMs implemented using block random-access memory (BRAM), lookup table RAM (LUTRAM), and flip-flops (FFs). BRAM-based TCAM suffers from the pre-processing of mapping data, requires the data to be in a specific order in some cases, and has a large SRAM/TCAM bit ratio. LUTRAM-based CAM/TCAM suffers from wide bit-wise ANDing, high routing complexity, but has a small SRAM/TCAM bit ratio of 14 compared to 16 in the case of BRAM-based TCAM. Shallow and wide RAM blocks are required to implement large-size RAM-based TCAMs (BRAM-based and LUTRAM-based TCAMs). FF-based TCAMs use FFs as their memory elements and have reduced hardware costs per TCAM bit. However, due to the routing complexity, it suffers from scalability and a large amount of power consumption. The update latency of BRAM-based TCAM and LUTRAM-based TCAM is proportional to the depth of BRAM and LUTRAM, respectively. However, FF-based CAM updates in 1 or 2 clock cycles depending on the availability of input/output pins on target FPGA.

Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA

The quasi-cyclic (QC) low-density parity-check (LDPC) code is a key error correction code for the fifth generation (5G) of cellular network technology. Designed to support several frame sizes and code rates, the 5G LDPC code structure allows high parallelism to deliver the high demanding data rate of 10 Gb/s. This impressive performance introduces challenging constraints on the hardware design. Particularly, allowing such high flexibility can introduce processing rate penalties on some configurations. In this context, a novel highly parallel and flexible hardware architecture for the 5G LDPC decoder is proposed, targeting field-programmable gate array (FPGA) devices. The architecture supports frame parallelism to maximize the utilization of the processing units, significantly improving the processing rate. The controller unit was carefully designed to support all 5G configurations and to avoid update conflicts. Furthermore, an efficient data scheduling is proposed to increase the processing rate. Compared to the recent related state of the art, the proposed FPGA prototype achieves a higher processing rate per hardware resource for most configurations.

LabVIEW-FPGA-Based Real-Time Data Acquisition System for ADITYA-U Heterodyne Interferometry

Microwave interferometry has been used extensively for plasma diagnostics in tokamak for real-time electron density measurements. Real-time density measurement is an indispensable part of advanced tokamaks, as it can be used as feedback to control the plasma operation. In this article, we report the development of the phase extraction method in a heterodyne interferometer for real-time density estimation using a field-programmable gate array (FPGA). FPGA provides parallel processing, minimum control delay, more efficient processing architecture, and jitter-free synchronization between different control layers. Digital CORDIC algorithm is used for the estimation of the phase between two arms of the interferometer. A LabVIEW program is developed for the FPGA target and host controller to acquire the data and estimate electron density in real time, which can be used for feedback purpose by regulating the amount of gas injection using piezoelectric valve that requires a high voltage (~100 V) for about 1 ms. The delay in generating the feedback signal is proportional to the sampling speed (100 kHz) of the analog signal. In this work, line-averaged electron density measurement using digital signal processing (DSP) and LabVIEW-FPGA technology is presented. The developed interferometer and data acquisition (DAQ) system installed on ADITYA-U tokamak can measure the electron density in the range of $1 \times 10^{18} - 1 \times 10^{20}\,\,\text{m}^{-3}$ . The algorithm used for the estimation of phase difference is validated using a conventional arctan method. The developed reconfigurable FPGA-based DAQ system uses low power, has a reconfigurable hardware structure for fast real-time signal processing, and can be easily upgraded.

Advancing synthesis of decision tree-based multiple classifier systems: an approximate computing case study

So far, multiple classifier systems have been increasingly designed to take advantage of hardware features, such as high parallelism and computational power. Indeed, compared to software implementations, hardware accelerators guarantee higher throughput and lower latency. Although the combination of multiple classifiers leads to high classification accuracy, the required area overhead makes the design of a hardware accelerator unfeasible, hindering the adoption of commercial configurable devices. For this reason, in this paper, we exploit approximate computing design paradigm to trade hardware area overhead off for classification accuracy. In particular, starting from trained DT models and employing precision-scaling technique, we explore approximate decision tree variants by means of multiple objective optimization problem, demonstrating a significant performance improvement targeting field-programmable gate array devices.

Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators

With the diffusion of cyber-physical systems and internet of things, adaptivity and low power consumption became of primary importance in digital systems design. Reconfigurable heterogeneous platforms seem to be one of the most suitable choices to cope with such challenging context. However, their development and power optimization are not trivial, especially considering hardware acceleration components. On the one hand high level synthesis could simplify the design of such kind of systems, but on the other hand it can limit the positive effects of the adopted power saving techniques. In this work, the mutual impact of different high level synthesis tools and the application of the well known clock gating strategy in the development of reconfigurable accelerators is studied. The aim is to optimize a clock gating application according to the chosen high level synthesis engine and target technology (Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)). Different levels of application of clock gating are evaluated, including a novel multi level solution. Besides assessing the benefits and drawbacks of the clock gating application at different levels, hints for future design automation of low power reconfigurable accelerators through high level synthesis are also derived.

Hardware Architecture Proposal for TEDA Algorithm to Data Streaming Anomaly Detection

The amount of data in real-time, such as time series and streaming data, available today continues to grow. Being able to analyze this data the moment it arrives can bring an immense added value. However, it also requires a lot of computational effort and new acceleration techniques. As a possible solution to this problem, this paper proposes a hardware architecture for Typicality and Eccentricity Data Analytic (TEDA) algorithm implemented on Field Programmable Gate Arrays (FPGA) for use in data streaming anomaly detection. TEDA is based on a new approach to outlier detection in the data stream context. The suggested design has a full parallel input of N elements and a 3-stage pipelined architecture to reduce the critical path and thus optimize the throughput. In order to validate the proposals, results of the occupation and throughput of the proposed hardware are presented. The design reached a speed of up to 693x, compared to other software platforms, with a throughput of up to 10.96 MSPs (Mega Sample Per second), using a small portion of the target FPGA resources. Besides, the bit accurate simulation results are also presented. This work is a pioneer in the hardware implementation of the TEDA technique in FPGA. The project aims to Xilinx Virtex-6 xc6vlx240t-1ff1156 as the target FPGA.

Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs

The increasing size of modern field programmable gate arrays (FPGAs) allows for ever more complex applications to be mapped onto them. However, long design implementation times for large designs can severely affect design productivity. A modular design methodology can improve design productivity in a divide and conqueror fashion but at the expense of degraded performance and power consumption of the resulting implementation. To reduce the dominant power dissipation component in FPGAs, the routing power, methodologies have been proposed that consider data communication between modules during module formation and placement on the FPGA. Selecting proper mapping region on target FPGAs, on the other hand, is becoming a critical process because of the heterogeneous resources and column arrangements in modern FPGAs. Selecting inappropriate FPGA regions for mapping could lead to degraded performance. Hence, we propose a methodology that uses communication-aware module placement, such that modules are mapped by selecting the best shape and region on the FPGA factoring the columnar resource arrangements. Additionally, techniques for module locking and splitting have been proposed for deterministic convergence of the algorithm and for improved module placement. This methodology exhibits nearly 19% routing power reduction with respect to commercial CAD flows without any degradation in achievable performance.

Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm

Harris corner detection is an algorithm frequently used in image processing and computer vision applications to detect corners in an input image. In most modern applications of image processing, there is a need for real time implementation of algorithms such as Harris corner detection in hardware systems such as field-programmable gate arrays (FPGAs). FPGAs allow faster algorithmic throughput, which is required to match real time speeds or cases where there is a requirement to process faster data rates. High level synthesis tools offer higher abstraction level to designers with continued verification during the design flow and hence are getting popular with the design community. This paper proposes a high speed and area optimized implementation of a Harris corner detection algorithm. The proposed implementation was actualized using a novel high-level synthesis (HLS) design method based on application-specific bit widths for intermediate data nodes. Register transfer level (RTL) code was generated using MATLAB HDL coder for HLS. The generated hardware description language (HDL) code was implemented on Xilinx ZedBoard using Vivado software and verified for functionality in real time with input video stream. The obtained results are superior to those of previous implementations in terms of area(smaller gate count on target FPGA) and speed for the same target board.