Filter Taps Research Articles

Experimental demonstration of 10 Gb/s multi-level carrier-less amplitude and phase modulation for short range optical communication systems

Carrier-less amplitude and phase (CAP) modulation can be a good candidate for short range optical communications for considerable computational complexity reduction and simple system structure. In this paper, a detailed investigation on the digital filters in CAP modulation system is presented. An adaptive equalizer based on cascaded multi-modulus algorithm (CMMA) is used for the demodulation at the receiver. The impact of digital filter taps on system performance is investigated through comprehensive simulations and a 10 Gb/s CAP16 modulation system is demonstrated experimentally. The BER performance for different length of fiber link is measured. Compared with back-to-back (BTB) transmissions, 2 dB and 3.5 dB receiver power penalty are observed at BER of 10(-3) for 20 km and 40 km fiber link respectively. It clearly demonstrates the feasibility of the CAP16 modulation for the short range transmission systems.

Fast and Accurate Direct MDCT to DFT Conversion With Arbitrary Window Functions

In this paper, we propose a method for direct conversion of MDCT coefficients to DFT coefficients, without passing through time signal reconstruction. In contrast to previous works, this method is valid for any pair of MDCT and DFT window functions. It is based on the decomposition of the MDCT-to-DFT conversion matrices into a Toeplitz part plus a Hankel part. The latter is split, then mirrored and combined with the former to construct a global Toeplitz matrix. This leads to a fast FIR filtering implementation of the conversion process. The filter taps are DFT coefficients of window functions products, and concentrate most of their energy in a few low-frequency taps. The conversion can thus be efficiently approximated by keeping only a few most significant taps, as confirmed by numerical experiments: For example, for frame size of 2048, Hanning-windowed DFT is obtained from KBD-windowed MDCT with SNR over 60 dB when keeping only 20 taps.

Channel Equalization of WCDMA Downlink System Using Finite Length MMSE-DFE

The performance of WCDMA system deteriorates in the presence of multipath fading environment. Fading destroys the orthogonality and is responsible for multiple access interference (MAI). Though conventional rake receiver provides reasonable performance in the WCDMA downlink system due to path diversity, but it does not restores the orthogonality. Linear equalizer restores orthogonality and suppresses MAI, but it is not efficient, since its performance depends on the spectral characteristics of the channel. To overcome this, Minimum Mean Square Error- Decision Feedback Equalizer (MMSE-DFE) with a linear, anticausal feedforward filter, causal feedback filter and simple detector is proposed in this paper. The filter taps of finite length DFE is derived using the cholesky factorization theory, capable of suppressing noise, Intersymbol Interference (ISI) and MAI. This paper describes the WCDMA downlink system using finite length MMSE-DFE and takes into consideration the effects of interference which includes additive white gaussian noise, multipath fading, ISI and MAI. Furthermore, the performance is compared with conventional rake receiver and MMSE and the simulation results are shown. Keywords - MMSE, MMSE-DFE, rake receiver, WCDMA

Two Blind Adaptive Equalizers Connected in Series for Equalization Performance Improvement

A variable step-size parameter is usually used to accelerate the convergence speed of a blind adaptive equalizer with N1 + N2 －1 coefficients where N1 and N2 are odd values. In this paper we show that improved equalization performance is achieved when using two blind adaptive equalizers connected in series where the first and second blind adaptive equalizer have N1 and N2 coefficients respectively compared with the case where a single blind adaptive equalizer is applied with N1 + N2 －1 coefficients. It should be pointed out that the same algorithm (cost function) is used for updating the filter taps for the different equalizers and that a fixed step-size parameter is used. Simulation results show that for the low signal to noise ratio (SNR) environment and for the case where the convergence speed is slow due to the channel characteristics, the new method has a faster convergence speed with a factor of approximately two while leaving the system with approximately the same or lower residual intersymbol interference (ISI).

Time Domain Blind I/Q Imbalance Compensation Based on Real-Valued Filter

This paper proposes a novel time domain blind compensation for frequency-independent and frequency-dependent I/Q imbalance in direct-conversion receivers. Analysis of a difference filter representing the frequency-dependent I/Q imbalance shows that the filter taps are tightly constrained by analog front-end image attenuation (IA). For practical front-ends with reasonable IA, it is proved that the difference filter is minimum phase. We also show that the magnitude response of the difference filter can be obtained from the branch signal autocorrelations. Then, the magnitude response can be used to determine the corresponding minimum phase response. Subsequently, from the cross-correlation of the branch signals, we can estimate the frequency-independent phase imbalance. Since the proposed method has an analytical solution, it can be easily implemented. Simulations of various scenarios confirm its validity and its superior compensation performance.

Efficient Complexity Reduction Technique for Parallel FIR Digital Filter based on Fast FIR Algorithm

The objective of the paper is to reduce the hardware complexity of higher order FIR filter with symmetric coefficients. The aim is to design efficient Fast Finite-Impulse Response (FIR) Algorithms (FFAs) for parallel FIR filter structure with the constraint that the filter tap must be a multiple of 2. In our work we have briefly discussed for L = 4 parallel implementation. The parallel FIR filter structure based on proposed FFA technique has been implemented based on carry save and ripple carry adder for further optimization. The reduction in silicon area complexity is achieved by eliminating the bulky multiplier with an adder namely ripple carry and carry save adder. For example, for a 6-parallel 1024-tap filter, the proposed structure saves 14 multipliers at the expense of 10 adders, whereas for a six-parallel 512-tap filter, the proposed structure saves 108 multipliers at the expense of 10 adders. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric coefficients from the existing FFA parallel FIR filter, especially when the length of the filter is very large.

Least squares channel estimation and adaptive equalization at low signal to noise ratios

Least squares based adaptive algorithms are among the most commonly used techniques for both channel estimation and adaptive equalization using signals that have propagated through underwater acoustic channels. Such channels are often characterized by long delay spreads meaning that the impulse response of the channel contains many “taps” or “weights” to be estimated or accommodated. In addition, the channel is often time varying which limits the duration of the averaging window that can be used by the algorithm’s adaptation process. At low SNRs, these two factors pose a significant challenge to algorithm performance. This challenge is particularly severe in the context of adaptive equalization where the use of multichannel equalizers is often required to achieve reliable performance and the traditional approach of joint optimization of the feedforward filter tap weights on all receiver channels results in large dimensional optimization problems. This talk will contrast and compare the impact of low SNR on least squares based channel estimation and adaptive equalization algorithms. The role of dimensionality reduction will be examined and the response of multichannel equalizers to different signal and noise environments as well under different equalizer configurations will be examined.

Photonic microwave finite impulse response filter using a spectrally sliced supercontinuum source

A novel photonic microwave discrete-time finite-impulse response filter is created by spectrally slicing a supercontinuum source, generated from a mode-locked laser. We experimentally demonstrate a four-tap filter with a 28.16 dB extinction ratio. Comparison between measured and predicted magnitude responses shows an excellent match in the performance of the notch filter across the entire bandwidth. The small amount of individual deviation points from the predicted response shows the stability of the amplitude fluctuations between each of the individual, spectral sliced filter taps.

Sparse approximation based resource allocation in DMT transmitters with per-tone pulse shaping

Per-tone pulse shaping has been proposed as an alternative to time domain spectral shaping for DMT transmitters. It shapes the spectrum of individual tones such that their stop band energy contribution can be minimized. In per-tone pulse shaping based DMT transmitters a fixed order non-sparse pulse shaping filter is typically used for every tone. Furthermore, no specific power loading scheme is used. However, the contribution of a particular tone to the stop band energy depends on the amount of power transmitted on the tone and the distance of the tone from the band edges. Tones with sufficiently low power as well as tones sufficiently away from the band edges could be assigned a sparse pulse shaping filter, which could then help to reduce the overall number of filter taps. In general the combination of power loading and sparse pulse shaping filters can be used to achieve a high data rate under given resource constraints. In this paper we present an algorithm to optimally allocate the available resources, i.e., power and filter taps, under PSD mask constraints, which is based on a dual problem formulation. This algorithm achieves a high performance with relatively low complexity, which is also demonstrated by simulations.

Using Bayesian inference for the design of FIR filters with signed power-of-two coefficients

The design approach presented in this paper applies Bayesian inference to the design of finite impulse response (FIR) filters with signed power-of-two (SPoT) coefficients. Given a desired frequency magnitude response specified by upper and lower bounds in decibels, Bayesian parameter estimation and model selection are adapted to produce a distribution of potential designs, all of which perform at or close to the specified standard. In the process, having incorporated prior information such as the maximum acceptable number of SPoT terms and filter length, and the practical design requirement to use the fewest bits possible, the total number of bits, filter taps and SPoT terms, and the filter length required in a design are automatically determined. The produced design candidates have design complexity appropriate to the design specifications and requirements, as designs with higher design complexity than required are rendered less probable by the embedded Ockham's razor. This innate ability is a prominent advantage that the newly developed framework possesses over many optimization based techniques as it leads to designs that require fewer SPoT terms and filter taps. Most importantly, it avoids the intricacy, arduousness and rigorousness involved in devising an appropriate scheme for balancing design performance against design complexity.

Development of signal processing system of avalanche photo diode for space observations by Astro-H

Astro-H is the sixth Japanese X-ray space observatory which will be launched in 2014. Two of onboard instruments of Astro-H, Hard X-ray Imager and Soft Gamma-ray Detector are surrounded by many number of large Bismuth Germanate (Bi4Ge3O12; BGO) scintillators. Optimum readout system of scintillation lights from these BGOs are essential to reduce the background signals and achieve high performance for main detectors because most of gamma-rays from out of field-of-view of main detectors or radio-isotopes produced inside them due to activation can be eliminated by anti-coincidence technique using BGO signals. We apply Avalanche Photo Diode (APD) for light sensor of these BGO detectors since their compactness and high quantum efficiency make it easy to design such large number of BGO detector system. For signal processing from APDs, digital filter and other trigger logics on the Field-Programmable Gate Array (FPGA) is used instead of discrete analog circuits due to limitation of circuit implementation area on spacecraft. For efficient observations, we have to achieve as low threshold of anti-coincidence signal as possible by utilizing the digital filtering. In addition, such anti-coincident signals should be sent to the main detector within 5μs to make it in time to veto the A–D conversion. Considering this requirement and constraint from logic size of FPGA, we adopt two types of filter, 8 delay taps filter with only 2 bit precision coefficient and 16 delay taps filter with 8 bit precision coefficient. The data after former simple filter provides anti-coincidence signal quickly in orbit, and the latter filter is used for detail analysis after the data is down-linked.

An efficient post-processing filter for multi-channel acoustic echo cancellation system

The acoustic echo usually cannot be totally removed by the adaptive filter due to the insufficient filter taps, nonlinearity of the echo path transfer function, and the background noise. A post-processing filter, which aims to suppress the residual echo, thus plays an important role in the acoustic echo cancellation system. In this paper, an efficient post filter is proposed based on the coherence between the error signal and the echo estimation of the adaptive filter. The proposed method can be seamlessly combined with the multi-delay frequency-domain adaptive filter. Furthermore, it can be easily extended to multi-channel processing. The instrumental evaluation and listening test both demonstrate the superiority of the proposed method.

A Novel High Speed FPGA Architecture for FIR Filter Design

<em><strong> </strong></em>This paper presents the details of hardware implementation of linear phase FIR filter using merged MAC architecture. Speed of convolution operation of FIR filter is improved using merged MAC architecture. By exploiting the reduced complexity made possible by the use of sparse powers of two partial products terms coefficients, an FIR filter tap can be implemented with 2B full adders, and 2B latches, where B is intermediate wordlegnth. Word and bit level parallelism allows high sampling rates, limited only by the full adder delay. The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits. Increasing the speed of operation is achieved by using higher modified compressors in critical path. Our objective of work is, to increase the speed of multiplication and accumulation operation by minimizing the number of combinational gates using higher n: 2 compressors, which is required more for Array multiplier at the time of implementation of array architecture. This novel architecture allows the implementation of high sampling rate filters of significant length on FPGA Spartan-3 device (XC3S400 PQ-208). The simulation result shows convolution output of digital FIR filter which is done using Questa Sim 6.4c Mentor Graphics tool. The experimental test of the proposed digital FIR filter is done using Spartan-3 device (XC3S400 PQ-208)

Rapid method for viable Cryptosporidium parvum oocysts detection

Cryptosporidium parvum is a waterborne coccidian protozoan parasite known to infect humans, resulting in an illness known as cryptosporidiosis. The widely used USEPA method 1622 to detect Cryptosporidium is time consuming, and unable to provide the information on oocysts viability and species. In order to develop a fast detection method for viable C. parvum oocysts, a 0.2 μm pore size hollow fiber membrane and 0.45 μm pore size disc membrane were used to filter tap water. Modified Immunomagnetic separation (IMS) purification was followed, and the IMS condition was optimized to shorten the purification time. Finally, fluorescence in situ hybridization (FISH) and FITC-conjugated monoclonal antibody (FMAb) staining were combined to detect viable oocysts, and results indicated that the viable oocysts detection by FISH/FMAb can be achieved in 20 min. The total viable oocysts detection time can be shortened to less than 1.5 h without affecting oocysts recovery.

A dual-chain approach for bottom–up construction of wavelet filters with any integer dilation

A dual-chain approach is introduced in this paper to construct dual wavelet filter systems with an arbitrary integer dilation d⩾2. Starting from a pair (a,a˜) of d-dual low-pass filters, with (a0,a1)=(a,a˜), a top–down chain of filters a0→a1→⋯→ar=δ is constructed with consecutive d-dual pairs (aj,aj+1), j=1,…,r−1, and #(a1)>#(a2)>⋯>#(ar)=1, where δ(0)=1 and δ(k)=0 for all k∈Z\\{0}, and #(aj) denotes the number of filter taps of aj. This enables the formulation of the filter system (ar;br,1,…,br,d−1)=:(ar;b→r), with b→r=[δ(⋅−1),…,δ(⋅−d+1)], to be used as the second component of the initial filter system ((ar−1;b→r−1),(ar;b→r)) of the bottom–up d-dual chain: ((ar−1;b→r−1),(ar;b→r))→((ar−2;b→r−2),(ar−1;b→r−1♯))→⋯→((a0;b→0),(a1;b→1♯)), constructed bottom–up iteratively, from j=r to j=0, by using both the d-duality property of (aj,aj+1), j=0,…,r−1 and the unimodular property of the polyphase Laurent polynomial matrix associated with the filter system (aj;b→j). Then the desired dual wavelet filter systems, associated with a and a˜, are given by (b1,…,bd−1):=(b0,1,…,b0,d−1) and (b˜1,…,b˜d−1):=(b1,1♯,…,b1,d−1♯). More importantly, the constructive algorithm for this dual-chain approach can be appropriately modified to preserve the symmetry property of the initial d-dual pair (a,a˜). For any dilation factor d, the dual-chain algorithms developed in this paper provide two systematic methods for the construction of both biorthogonal wavelets and bottom–up wavelets with or without the symmetry property.

Soft-In Soft-Out DFE and Bi-Directional DFE

We design a soft-in soft-out (SISO) decision feedback equalizer (DFE) that performs better than its linear counterpart in turbo equalizer (TE) setting. Unlike previously developed SISO-DFEs, the present DFE scheme relies on extrinsic information formulation that directly takes into account the error propagation effect. With this new approach, both error rate simulation and the extrinsic information transfer (EXIT) chart analysis indicate that the proposed SISO-DFE is superior to the well-known SISO linear equalizer (LE). This result is in contrast with the general understanding today that the error propagation effect of the DFE degrades the overall TE performance below that of the TE based on a LE. We also describe a new extrinsic information combining strategy involving the outputs of two DFEs running in opposite directions, that explores error correlation between the two sets of DFE outputs. When this method is combined with the new DFE extrinsic information formulation, the resulting bidirectional turbo-DFE achieves excellent performance-complexity tradeoffs compared to the TE based on the BCJR algorithm or on the LE. Unlike turbo LE or turbo DFE, the turbo BiDFE's performance does not degrade significantly as the feedforward and feedback filter taps are constrained to be time-invariant.

A New Echo Cancellation Algorithm without Double-Talk Detection Based on Correlation Function

In an adaptive echo canceller, the detection algorithm able to distinguish echo path change (EPC) from double-talk (DT) is vital to ensure that adaptive filter tap coefficients are updated in case of EPC and frozen during the DT period. The paper presents a new echo cancel algorithm, which can protect the adaptive filter performance during double-talk in acoustic echo cancellation of teleconference without setting a detector. A judgment value can be directly used in the iteration formula to control the iteration speed of the filter, which composed of the correlation of the far-end signal and near-end received signal, the pre-correlation of the error signal. The computer simulation results verify that the mentioned algorithm has the good double talk protection performance, and it is very useful and efficient in distinguishing EPC from DT but with less computational complexity contrast to the congener algorithm.

Bipolar tap photonic microwave notch filter using electroabsorption modulator-integrated distributed feedback laser diodes in a parallel configuration

We propose a bipolar tap photonic microwave notch filter scheme, which can be used to realize a fully integrated, semiconductor-based notch filter. The scheme is based on two electroabsorption modulator (EAM)-integrated distributed feedback laser diodes in a parallel configuration. We show that two filter taps with opposite polarities can be readily obtained by using the negative and positive slopes of the U-shaped electro-optic transfer functions of the EAMs under special design and operating conditions. An experiment was carried out to verify the working principle of the proposed scheme. Notch frequency tuning was also demonstrated by varying the laser wavelength spacing; the spacing was varied by changing the temperature. A frequency tuning range of ~1.8 GHz with a notch depth of ~40 dB was achieved.

A 0.5 mm$^{2}$ Power-Scalable 0.5–3.8-GHz CMOS DT-SDR Receiver With Second-Order RF Band-Pass Sampler

A highly flexible receiver chain based on RF-sampling and discrete-time signal processing in the charge domain for SDR applications is presented. A compact switched-inductor variable-gain front-end provides multiband low noise amplification and RF-selectivity with reduced area penalties. Strong selectivity at RF was obtained through a novel discrete-time decimating bandpass filter with triangular weighted filter taps. Decimation filters with programmable number of taps offer flexible rate decimation. A power scalable discrete-time baseband filter was implemented in-order to minimize static power consumption. The 90-nm digital CMOS implementation achieves a noise figure of 5.1 dB, a variable gain range of more than 60 dB with +1 dBm IIP3 and +50 dBm IIP2. This is achieved for power figures competitive with dedicated solutions. The receiver, frequency synthesizer excluded, occupies only 0.5 mm2 .

Implementation of the Trigonometric LMS Algorithm using original CORDIC ROTATION

The LMS algorithm is one of the most successful adaptive filtering algorithms. It uses the instantaneous value of the square of the error signal as an estimate of the mean-square error (MSE). The LMS algorithm changes (adapts) the filter tap weights so that the error signal is minimized in the mean square sense. In Trigonometric LMS (TLMS) and Hyperbolic LMS (HLMS), two new versions of LMS algorithms, same formulations are performed as in the LMS algorithm with the exception that filter tap weights are now expressed using trigonometric and hyperbolic formulations, in cases for TLMS and HLMS respectively. Hence appears the CORDIC algorithm as it can efficiently perform trigonometric, hyperbolic, linear and logarithmic functions. While hardware-efficient algorithms often exist, the dominance of the software systems has kept those algorithms out of the spotlight. Among these hardware- efficient algorithms, CORDIC is an iterative solution for trigonometric and other transcendental functions. Former researches worked on CORDIC algorithm to observe the convergence behavior of Trigonometric LMS (TLMS) algorithm and obtained a satisfactory result in the context of convergence performance of TLMS algorithm. But revious researches directly used the CORDIC block output in their simulation ignoring the internal step-by-step rotations of the CORDIC processor. This gives rise to a need for verification of the convergence performance of the TLMS algorithm to investigate if it actually performs satisfactorily if implemented with step-by-step CORDIC rotation. This research work has done this job. It focuses on the internal operations of the CORDIC hardware, implements the Trigonometric LMS (TLMS) and Hyperbolic LMS (HLMS) algorithms using actual CORDIC rotations. The obtained simulation results are highly satisfactory and also it shows that convergence behavior of HLMS is much better than TLMS.