Tail Current Source Research Articles

Moderately compressed high‐swing class‐C/B VCO with accurate current control

A high-swing class-C/B VCO without tail current source has been proposed. Accurate current control and dynamic bias generation that are essential to robust start-up and class-C operation are achieved through mirroring VCO LDO current and comparing against bias current. The VCO oscillation amplitude is designed to be sufficiently large and the core transistors are compressed moderately, such that the oscillation amplitude is stable while the VCO operates in class-C mode. A prototype PMOS VCO in a 0.13 μm process demonstrated a measured VCO figure of merit of 192 dB at 4.7 GHz with 1.4 mA current and core VDD at 0.6 V.

A VGA Linearity Improvement Technique for ECG Analog Front-End in 65nm CMOS

This paper presents a 65[Formula: see text]nm CMOS low-power, highly linear variable gain amplifier (VGA) suitable for biomedical applications. Typical biological signal amplitudes are in the 0.5–100[Formula: see text]mV range, and therefore require circuits with a wide dynamic range. Existing VGA architectures mostly exhibit a poor linearity, due to very low local feedback loop-gain. A technique to increase the loop-gain has been explored by adding additional feedback to the tail current source of the input differential pair. Stability analysis of the proposed technique was undertaken with pole-zero analysis. A prototype of Analog Front End (AFE) has been designed to provide 25–50 dB gain, and post-layout simulations showed a 15[Formula: see text]dB reduction in the harmonic distortion for 20[Formula: see text]mV pk-pk input signal compared to the conventional architecture. The circuit occupies 3,108[Formula: see text][Formula: see text]m2 silicon area and consumes 0.43 [Formula: see text]A from a 1.2[Formula: see text]V power supply.

A 0.25-V fifth-order Butterworth low-pass filter based on fully differential difference transconductance amplifier architecture

This paper presents a fifth-order Butterworth low-pass filter based on the fully differential difference transconductance amplifier (FDDTA) building blocks. At first, the FDDTA has been stated and its operation has been evaluated. Then, a practical implementation using two fully differential inverter-based operational transconductance amplifiers (OTA) was investigated. This particular FDDTA implementation relies on two main features: the intrinsically matched transistors that assure similar transconductances and output conductances for both inverter-based OTA instances; and the inverter-based approach without internal nodes that reduces circuit complexity and power consumption since it requires no supplementary external calibration circuit such as tail current or bias voltage sources. Finally, the filter architecture, which consists of one inverter-based OTA input stage and five FDDTAs in a cascade connection has been evaluated, showing that it presents the expected fifth-order transfer function according to the Butterworth theory. The prototypes, implemented in a 130 nm CMOS process, operate in weak inversion supplied with 0.25 V and consumes 603 nW. Furthermore, they feature a DR of 57 dB in a 100 Hz bandwidth and a maximum THD of 54 dB, therefore, accomplishing specifications that suit for low-frequency applications.

A Supply Pushing Reduction Technique for <italic>LC</italic> Oscillators Based on Ripple Replication and Cancellation

In this paper, we propose a method to suppress supply pushing of an LC oscillator such that it may directly operate from a switched-mode dc–dc converter generating fairly large ripples. A ripple replication block (RRB) generates an amplified ripple replica at the gate terminal of the tail current source to stabilize the oscillator’s tail current and thus its oscillating amplitude. The parasitic capacitance of the active devices and correspondingly the oscillation frequency are stabilized in turn. A calibration loop is also integrated on-chip to automatically set the optimum replication gain that minimizes the variation of the oscillation amplitude. A 4.9–5.6-GHz oscillator is realized in 40-nm CMOS and occupies 0.23 mm2 while consuming 0.8–1.3 mW across the tuning range (TR). The supply pushing is improved to <1 MHz/V resulting in a low < −49-dBc spur due to 0.5–12-MHz sinusoidal supply ripples as large as 50 mVpp. We experimentally verify the effectiveness of the proposed technique also in face of saw-tooth, multi-tone, and modulated supply ripples.

A voltage tunable CMOS differential active resistor and its application

SummaryWe propose a novel CMOS differential voltage‐controlled equivalent active resistor based on a modified common‐source cross‐coupled pair. The equivalent resistance exhibited by the circuit can be tuned to be either positive or negative through the tail current, which is controlled by a bias voltage. The complete cell comprises four transistors, two resistors in addition to the bias voltage, and tail current source. Application to the design of oscillators is demonstrated by theoretical analysis, circuit simulations, and verified experimentally through measurements on prototypes implemented using discrete transistors.

Analysis and Design of Ultra-Wideband mm-Wave Injection-Locked Frequency Dividers Using Transformer-Based High-Order Resonators

A transformer-based high-order resonator is proposed to improve the locking range (LR) of the millimeter-wave injection-locked frequency dividers (ILFDs). The LR limitations on ILFDs are discussed, and the operating principles of the proposed high-order resonator are analyzed based on their flattened phase response. The inductive gain peaking technique and the tail current source requirement are further analyzed for low power considerations. Two chips are fabricated in a 65-nm CMOS process to implement the proposed techniques: the first one measures an LR of 62.9% from 27.9 to 53.5 GHz while consuming 5.8 mW from a 1-V power supply and the second chip achieves an LR of 62.7% from 32.4 to 61.9 GHz while consuming only 1.2 mW from a 0.42-V power supply. The best figure of merit can achieve up to 24.7 GHz/mW.

A 53 dB&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\Omega~7$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-GHz Inductorless Transimpedance Amplifier and a 1-THz+ GBP Limiting Amplifier in 0.13-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;m CMOS

An inductorless 10-Gb/s optical receiver including a novel transimpedance amplifier (TIA) with dual feedback loop and a limiting amplifier with third-order nested feedback is presented. The current-buffer-based TIA employs an active Cherry-Hooper stage in the auxiliary amplifier and reuses the tail current source to achieve 10 Gb/s operation in the presence of a 1 pF photodiode input capacitance. Systematic analysis and design methodology of the double loop TIA is given with simple design equations derived for optimizing the performance of each loop. The use of nested feedback in the four stage limiting amplifier enables a gain-bandwidth-product >1 THz without the use of on-chip inductors. It is shown that the proposed limiting amplifier circuit enhances bandwidth by utilizing inherent equalization between the overdamped and underdamped poles. Implemented in IBM 130-nm CMOS technology, the optical receiver achieves a BER $ at 10 Gb/s for an input current of $30\,\,\mu \text{A}_{\mathrm{ p-p}}$ in electrical measurement, delivering 600 mV $_{\mathrm{ p-p}}$ at the output of the 50- $\Omega $ buffer. Optical testing confirmed −17.4 dBm sensitivity for a data rate of 7.5 Gb/s, which is limited by the maximum speed of the 850-nm source available at the time of measurement. The receiver dissipates 108 mW from 1.2-V supply (excluding the output buffer) and occupies a core area of only 0.08 mm2.

0.18 mW/pole inverter‐based G m ‐C bandpass filter with automatic frequency tuning

A low-power Gm-C filter with the elliptic prototype targeting wireless application of the IEEE 802.15.4 (ZigBee) standard is presented. A modified inverter-based Gm cell is proposed to increase the current efficiency. Due to the tail current source, this Gm cell also shows better common-mode rejection and power supply rejection performance than traditional operational transconductance amplifier (OTA) structure. The filter is implemented in a 65 nm CMOS process. It achieves a figure of merit of 0.01 fJ with a power consumption of 0.18 mW/pole from a 1.2 V supply voltage. It provides stopband attenuation better than 40 dB, and an in-band IIP3 of 9 dBm. An automatic frequency tuning circuit based on sine-wave PLL method is introduced to compensate for the process variations. The centre frequency and bandwidth can be simultaneously tuned to satisfy the specifications. They are also stable over the process variations with only 2.3% deviation.

A CMOS 6–10 GHz impulse radio UWB transmitter based on gated oscillator with switching pulse shaper

In an impulse radio ultra-wideband (IR-UWB) system for low-power location-aware sensor networks, the output pulses must meet the FCC spectral emission mask. In addition, to increase battery life, the IR-UWB transmitter must be energy efficient. In this paper, a CMOS ultra-wideband (UWB) transmitter designed using a 0.11-μm process is presented for 6–10 GHz applications. To reduce energy consumption, the transmitter adopts a gated voltage-controlled oscillator (VCO) that directly drives 50 Ω output impedance. A gated VCO that uses a trapezoidal pulse for on/off gating of the tail current source satisfies the spectrum mask without requiring an additional pulse shaping filter. The active energy consumption is 13.4 pJ/pulse at a pulse repeating frequency (PRF) of 40 MHz. The side-lobe rejection performance is more than 30 dB.

Phase noise model of ring oscillator under reduced supply with application to a time to digital converter

This paper investigates the phase noise of voltage controlled ring oscillators. The delay cell is a differential pair with no tail current source, suitable for reduced supply voltage as technology scales. As N, number of stages, decreases, the output can become unsaturated, introducing extra correlation and adding phase noise. The new phase noise model is developed (focusing on N = 2), which improves on impulse sensitivity function, Using a 0.13 μm CMOS technology in 1.2 V supply, this model is applied to the delay cell under different circuit parameters (focusing on tuning) and operating conditions, with theoretical results agreeing with simulations. The design was fabricated in 0.13 μm CMOS, and operates at 0.89 GHz oscillator frequency, and has 200 μW power consumption. To study the phase noise when the VCO is tuned, measurements at the boundary of typical tuning range is performed and agree with theory and simulations. Insights, based on theory, are presented and explain trends of simulated and measured phase noise. Next the ring oscillator is applied to a time to digital converter (TDC). Using the above noise model, the jitter of the VCO is calculated and then apply to calculate the resulting jitter in the TDC. Then the TDC is simulated with Matlab, with VCO jitter injected, and find reasonable comparison with theory.

Phase Noise of Unsaturated Two-Stage Voltage-Controlled Ring Oscillator Without Tail Current

This paper investigates the phase noise (PN) of two-stage voltage-controlled ring oscillators. The delay cell is source-coupled pair with no tail current source, suitable for reduced voltage swing as supply reduces under technology scaling. With two stages, the output can become unsaturated, introducing extra cycle-to-cycle correlation and adding PN. The new cycle-to-cycle PN model is developed and applied to two different cell topologies. The design was fabricated in 1.2-V 0.13- $\mu \text{m}$ CMOS, operating at 0.89-GHz oscillator frequency with 200- $\mu \text{W}$ power consumption. PN measurement and simulation agree with theory over circuit parameter variations and corresponding design insights are drawn. Specifically as tuning voltage varies from 0.5 to 0.6 V, PN increases by around 5 dB.

Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement

This brief presents the design of a single-stage amplifier with enhanced gain and speed, without the need for using any cascode devices, positive feedback, or feed forward technique. Instead, two voltage-combiners replace the traditional tail current source, commonly employed to bias the differential pair. The resultant topology shows both additional dc gain and a gain bandwidth product enhancement. Simulation results of a properly optimized circuit, using AIDA-C, a state-of-the-art multi-objective multi-constraint IC sizing and optimization tool, demonstrate that a dc gain above 47 dB and a figure-of-merit better than 960 MHz*pF/mA, in corner conditions, can be achieved with this topology, in the UMC 130-nm technology. The circuit was fabricated and experimentally measured, showing an energy-efficiency figure-of-merit of 1023.6 MHz*pF/mA.

Low phase noise LC VCO with sinusoidal tail current shaping using cascode current source

Tail current shaping is a known technique for phase noise reduction. According to this technique, close to outputs zero crossing points, where Impulse Sensitivity Function (ISF) is maximum, current supplying path to the transistor pair is disconnected. In this paper, tail current shaping is performed by two additional transistors that are placed in cascode configuration with the tail current source. Conventional tail current shaping is performed by two tail transistors with the gates connected to the oscillator outputs. The proposed circuit outperforms the conventional circuit in phase noise performance, due to four mechanisms: higher impedance seen from the common source of switching transistors due to cascode current source; better tail current shaping; higher oscillation amplitude with the same power consumption; and lower RMS value of the effective ISF. Also, the proposed circuit presents more stable bias point and output amplitude, compared to conventional circuit. In addition, higher ratio of start-up tail current to the minimum of shaped tail current for the proposed circuit, removes the need for additional start-up detection circuits. Post layout simulations predict a sample oscillator designed at 4GHz in 0.18µm RF CMOS technology presents 11.3 and 3.8dB less phase noise at 1MHz offset, compared to simple and conventional oscillators, respectively.

A 0.4 $\mu \text{g}$ Bias Instability and 1.2 $\mu \text{g}/\surd $ Hz Noise Floor MEMS Silicon Oscillating Accelerometer With CMOS Readout Circuit

This paper describes a silicon-on-insulator MEMS oscillating accelerometer with a fully differential CMOS continuous-time oscillation sustaining circuit and a digital frequency measurement circuit. To reduce the amplitude-stiffness-induced frequency variation, the effects of flicker noise in the automatic amplitude control circuit are classified into additive and multiplicative components, which are suppressed by chopper stabilization and tail current source free structures, respectively. A low-power digital frequency measurement circuit employing a time-domain $\Sigma \Delta $ ADC is integrated on chip. The accelerometer achieves a bias instability of 0.4/2 $\mu \text{g}$ , a bias stability of 4.13/13.2 $\mu \text{g}$ , and a noise floor of 1.2/2.6 $\mu \text{g} / \surd $ Hz, as measured from the analog/digital outputs, respectively, with a scale factor of 280 Hz/g and a full scale of ±20 g. The chip is fabricated in 0.35 $\mu \text{m}$ standard CMOS technology, and consumes 4.37 mW under a 1.5 V supply.

A Low Phase Noise NMOS LC-VCO using New Degeneration Structure

Background/Objectives: It is necessary to reduce the contribution of a differential pair for a low phase noise LC-VCO because previous works are mainly focused on the LC tank and tail current source. Methods/Statistical Analysis: A new NMOS LC-VCO with an LC degenerated structure is proposed for linearizing a cross coupled differential pair. The NMOS LC-VCO with the proposed structure is designed using a 0.18 μm CMOS process and simulated by Spectre RF. Findings: The proposed structure is very useful for suppressing the flicker and thermal noise contribution of a cross coupled differential pair which forms a negative transconductance. Especially, the proposed structure overcomes the limitation the previous capacitive degeneration structure when it operates at higher oscillator frequency above 5 GHz. Application/Improvements: Its phase noise performance is improved about 3 dB compared with that of the conventional NMOS LC-VCO structure with no degeneration consuming the same bias current of 2mA from a 1.8 V supply.

Multiband multistandard frequency synthesizer for mobile TV tuner with LC‐VCO by digital AAC

ABSTRACTTo improve the phase noise (PN) degradation from the tail current source, this article presents an inductor‐capacitor voltage‐controlled oscillator (LC‐VCO) with digitally controlled programmable low drop out. The digital automatic amplitude calibration (AAC) loop is successively implemented to make the voltage swing constant over 900–1940 MHz. A 40–970 MHz frequency synthesizer with switching dividers is implemented to support the operating frequency range of the multiband mobile TV tuners. The PN of −130 dBc/Hz @ 1 MHz offset is obtained at 474 MHz. The PN variation by the help of AAC loop is measured &lt;2.4 dB over −40–85°C. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1838–1841, 2016

Low-phase-noise CMOS VCO with new drain–gate feedback path

In this paper a new LC oscillator without tail current source with an impedance transformation block (ITB) has been presented. Using this ITB, the noise generation from active devices is reduced. The cross-coupled transistors remain mostly in the saturation region and prevent decreasing of LC-tank quality factor. Moreover this structure benefits from more relaxed start-up condition as compared to the conventional LC oscillators and preserves its low phase-noise performance even in low voltage operation. This oscillator is designed and simulated in 0.18 µm CMOS process. The simulation results show that the proposed oscillator achieved a phase noise between ź138.5 and ź141.2 dBc/Hz at 3 MHz frequency offset with 23 % tuning range between 4.61 and 5.79 GHz. The corresponding Figure-of-merit in this tuning range is between ź189.1 and ź192.1 dBc/Hz which is among the best reported performance in comparison to the other state of the arts designs.

A COMPARATIVE STUDY OF DIFFERENT TYPES OF MIXER TOPOLOGIES

In this paper, a comparative study of different types of mixer topologies is presented. Gilbert cell is widely used as core of the mixer because it provides high conversion gain, good port-to-port isolation and low even-order distortion. It is found that the linearity of mixer is very good for Multi-Tanh technique by incorporating multiple differential trans-conductance stage but it reaches to very low conversion gain whereas, use of current bleeding technique increase linearity and conversion gain of the mixer by adding current source to increase the bias current at the expense of power consumption. A very low value of noise figure can be achieved with the switched biasing technique by replacing current source with parallel connected nMOS transistors but due to use of the transistor in place of tail current source, linearity is degraded and more power is consumed. Folded Cascode Technique is used to reduce DC supply voltage by folding the LO switching stage with pMOS transistors in switching stage but it degrades the noise figure. Bulk-driven technique can be employed to lower down the power consumption by providing the switching action via the gate of LO (RF) and amplification by the bulk of LO (RF) transistors, however it reduces the linearity. High linearity is obtained by using CCPD (Cross coupled post distortion) technique by cancelling of third order derivatives but it decreases the conversion gain and consume more power due to increase in the number of auxiliary transistors. MGTR enables to achieve high linearity by incorporating auxiliary transistor but it decreases the overall conversion gain and increases noise figure of the mixer. So it is observed that there is a trade-off among the performance metrics, i.e., conversion gain, noise figure linearity, and power consumption of the mixer.

80-GHz-band low-power sub-harmonic mixer IC with a bottom-LO-configuration in 130-nm SiGe BiCMOS

In this paper, a W-band (80 GHz) sub-harmonic mixer (SHM) IC is designed, fabricated and measured in 130-nm SiGe BiCMOS technology. The presented SHM IC makes use of a common emitter common collector transistor pair structure with a bottom-LO-configuration to decrease the LO power requirement and a tail current source to flatten the conversion gain. On-chip Marchand balun is designed for W-band on-wafer measurements. The SHM IC presented in this paper has exhibited a conversion gain of 3.9 dB at 80 GHz RF signal with an LO power of only −7 dBm at 39.5 GHz. The mixer core consumes only 0.68 mA at a supply voltage of 3.3 V.

0.6‐V 2.1‐mW RF receiver based on passive mixing and master–slave common‐mode rejection technique in 65 nm CMOS

A 0.6-V 2.1-mW RF receiver with regular threshold transistors is presented. A passive mixer which is built on low-power current-buffer is designed to build the RF front-end. A master–slave operational trans-conductance amplifier (OTA) structure which provides sufficient common-mode rejection ratio (CMRR) by auto-adjusting the gate of the triode-region biased tail current source is proposed as the building block of the intermediate-frequency (IF) modules. The proto-type of the RF receiver is designed and fabricated in Semiconductor Manufacturing International Corporation (SMIC) 65 nm CMOS process. The measurement indicates that the receiver covers a bandwidth from 1 to 1.5 GHz, achieving a voltage gain of 32 dB and a noise figure (NF) of 10 dB.