Table Memory Research Articles

Non-tables look-up search algorithm for efficient H.264/AVC context-based adaptive variable length coding decoding

In general, context-based adaptive variable length coding (CAVLC) decoding in H.264/AVC standard requires frequent access to the unstructured variable length coding tables (VLCTs) and significant memory accesses are consumed. Heavy memory accesses will cause high power consumption and time delays, which are serious problems for applications in portable multimedia devices. We propose a method for high-efficiency CAVLC decoding by using a program instead of all the VLCTs. The decoded codeword from VLCTs can be obtained without any table look-up and memory access. The experimental results show that the proposed algorithm achieves 100% memory access saving and 40% decoding time saving without degrading video quality. Additionally, the proposed algorithm shows a better performance compared with conventional CAVLC decoding, such as table look-up by sequential search, table look-up by binary search, Moon’s method, and Kim’s method.

A dsPIC based novel digital sinusoidal pulse-width modulation technique for voltage source inverter applications

This paper presents a novel digital sinusoidal pulse-width modulation (SPWM) technique based on immediate calculation of duty cycle count (DCC) values of pulses with high speed Harvard architecture based RISC controllers. The DCC values are calculated with the multiplication of an instant modulation index count (MIC) and a preloaded sine count value (SCV) table in the program memory of the controller. The proposed technique overcomes the drawbacks of overhead time in digital carrier-reference based technique and large memory requirement in look-up table technique. The proposed technique is effective where frequent change of modulation index (MI) of SPWM is essential like grid-connected inverter applications. The effectiveness of the proposed technique is verified with both Proteus VSM based simulation and dsPIC based experiment.

A high-efficient tables memory access saving algorithm for CAVLC decoding

Frequent table look-up can result in high memory access, and high memory access can cause increased power consumption in CAVLC decoding. Aiming to solve the problem of high table memory access during the process of CAVLC decoding for H.264/AVC due to frequent table look-up, thereby reducing the power consumption, a high-efficient table memory access saving algorithm is presented in this paper. The contribution of the proposed scheme is that we use program code to instead of the conventional table look-up method that requires a lot of memory access. In our scheme, we use program code to realize fully the expression of all the UVLT (Unstructured Variable Length Tables) in CAVLC decoding, as a result, all the decoded codewords in UVLT can be obtained easily through a program execution way instead of sequential table look-up. which can save a lot of memory access and power consumption due to without looking up UVLT in CAVLC decoding, The simulation results show that our proposed scheme can save 100 % memory access of table look-up for CAVLC decoding compared with TLSS method due to the use of program code, thereby saving much power consumption, without degrading video quality.

A High Efficient Tables Look-up Algorithm for CAVLC Decoding

In order to solve the problems of high table memory access and long table look-up time and big table storage space in the process of CAVLC decoding for H.264/AVC, a high efficient table look-up algorithm is presented in this paper. The contribution of this paper lies that we uses a program method to realize fully the no-table looking-up of codeword. Specifically, after finding the relationships existed in code length and numbers of 0 in code prefix and code suffix and code, we uses a program code method to realize entirely UVLCTs(Unstructured Variable Length Coding Tables) in CAVLC decoding, As a result, all decoded codewords in UVLCTS can be decoded and obtained easily through a program execution way instead of TLSS(table look-up by sequential search), which could save a lot of table memory access and reduce amount of table look-up time and save a large number of table storage spaces for CAVLC decoding. The simulation results show that our proposed scheme can save 100% table memory access, reduce about 45% table look-up time and save 2320 byte table storage space of table look-up in CAVLC decoding compared with TLSS method, without degrading video quality. Index Terms—Memory access; Table look-up; Storage space; CAVLC decoding; Program method

TurboLock: increasing associativity of lock table in transactional memory

Transactional memory (TM) is emerging as a promising paradigm to simplify parallel programming for chip multiprocessors. Most of software transactional memory (STM) systems exploit a lock table to synchronize transactional accesses to the shared memory locations. Memory addresses map to entries of the lock table through a hash function to detect conflicts in the event of simultaneous accesses to the shared memory locations. In the current implementation of the lock table, if two distinct addresses map to the same entry of the table, they are treated as a conflict even though there is no true conflict between the two addresses. This is called false conflict. In the event of a false conflict, transactions are aborted conservatively which reduces concurrency level in programs. In this paper, we study false conflicts in STMs and propose TurboLock to reduce frequency of false conflicts. Inspired by set associative caches, TurboLock increases associativity of the lock table to reduce likelihood of aliasing-induced conflicts. While TurboLock is effective in reducing the false conflicts, it may degrade performance due to overhead of the associative lock table in software. To improve performance of TurboLock, we propose HW-TurboLock which exploits hardware to reduce overhead of the associative lock table. We have evaluated our optimization techniques using Gem5 full-system simulator and compared the performance of the new implementation with the baseline scheme. Our simulation results reveal that HW-TurboLock is highly effective and significantly improves performance of TM systems.

A Tables Look-up Algorithm based on Program Code for CAVLC Decoding

Aiming to solve the problem of high memory access and long table look-up time in table look-up of CAVLC (Context-based Adaptive Variable Length Coding ) for H.264/ AVC , a efficient look-up algorithm based on program code is presented in table look-up for CAVLC decoding in this paper, based on the analysis of the structure of CAVLC code table .The basic idea of this algorithm is that a method based on program code is designed to express fully all the VLCTs (unstructured Variable Length Coding Tables ) in CAVLC decoding. As a result, the decoded codeword in VLCTs can be gotten easily in a program execution way which can save a lot of memory access and table look-up time spent in CAVLC decoding. The simulation results show that the proposed scheme can not only save 100% memory access of table look-up in CAVLC decoding, but also reduce 45% table look-up time in CAVLC decoding without degrading video quality, only adding 2.7kb storage space.

A look-up-table digital predistortion technique for high-voltage power amplifiers in ultrasonic applications

In this paper, we present a digital predistortion technique to improve the linearity and power efficiency of a high-voltage class-AB power amplifier (PA) for ultrasound transmitters. The system is composed of a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), and a field-programmable gate array (FPGA) in which the digital predistortion (DPD) algorithm is implemented. The DPD algorithm updates the error, which is the difference between the ideal signal and the attenuated distorted output signal, in the look-up table (LUT) memory during each cycle of a sinusoidal signal using the least-mean-square (LMS) algorithm. On the next signal cycle, the error data are used to equalize the signal with negative harmonic components to cancel the amplifier's nonlinear response. The algorithm also includes a linear interpolation method applied to the windowed sinusoidal signals for the B-mode and Doppler modes. The measurement test bench uses an arbitrary function generator as the DAC to generate the input signal, an oscilloscope as the ADC to capture the output waveform, and software to implement the DPD algorithm. The measurement results show that the proposed system is able to reduce the second-order harmonic distortion (HD2) by 20 dB and the third-order harmonic distortion (HD3) by 14.5 dB, while at the same time improving the power efficiency by 18%.

Effective reduction of the novel look-up table memory size based on a relationship between the pixel pitch and reconstruction distance of a computer-generated hologram

In this paper, we propose an approach, new to our knowledge, to effectively generate and reconstruct the resolution-enhanced computer-generated hologram (CGH) of three-dimensional (3-D) objects with a significantly reduced in memory size novel look-up table (N-LUT) by taking into account a relationship between the pixel pitch and reconstruction distance of the hologram pattern. In the proposed method, a CGH pattern composed of shifted versions of the principal fringe patterns (PFPs) with a short pixel pitch can be reconstructed just by using the CGH generated with a much longer pixel pitch by controlling the hologram reconstruction distance. Accordingly, the corresponding N-LUT memory size required for resolution-enhanced hologram patterns can be significantly reduced in the proposed method. To confirm the feasibility of the proposed method, experiments are carried out and the results are discussed.

Building Sequence Span Attribute Model and Example Analysis

∗ Corresponding Author: shisungu@126.com Abstract-Parallel parsing is one of the key technologies of parallel system. Grammatical character affects the efficiency of parallel parsing and degree of difficulty of implement. Existing methods have problems as follows: Parallelism of grammar that adapt different data object is difference, if there is a large difference between considering attribute and analysis object structure, then affect efficiency. Specific grammar parallel parsing is systematically studied. Scanning parallel parsing methods from the new angle of sequence span after word lattice distortion. Considering sequence span attribute between some specific grammars makes parsing without changing structure and data of CYK table based on the structure of word lattice CYK initialization table; In passing item of the form [i , j , B η·] in parallel parsing item table memory structure in circle structure is adopted chain breaking technology; When indexed optimize analysis, the key algorithms of increasing the feasibility and validity of sequence span attribute、reusing parsing tree、calculating of d space function and node separating are further studied, then unification and optimize effect between analysis table middle structure and data object structure is reached. New algorithm and implement strategy of parallel parsing of specific grammar is proposed.

Application and Research of Rotate-Lookup-Summation in Robot Motion

How to exercise reasonable motion control on robot becomes a new research focus in robot technology research. This paper proposes the Rotate-Lookup-Summation according to the deficiency of traditional look-up table. This method first confirm the controlling factors P1，P2….Pn that would affect the control volume Z, and then the multi-dimensional control volumes and multi-dimensional control factors would be projected to sub-dimensional space. Finally, the same controlling factors of different sub-dimensional space would be rotated to a single sub-dimensional space and establish a corresponding table. According to the single sub-dimensional space value of the controlling factors, the corresponding control variable could be found in table and eventually complete the control process. Experiments show that the method could ensure the integrity and accuracy of table, reduce the table memory capacitance and lookup time, so as to realize the control of look-up table in micro-device.

Weakly-Constrained Codes for Suppression of Patterning Effects in Digital Communications

We propose weakly-constrained stream and block codes with tunable pattern-dependent statistics and demonstrate that the block code capacity at large block sizes is close to the the prediction obtained from a simple Markov model published earlier. We demonstrate the feasibility of the code by presenting original encoding and decoding algorithms with a complexity log-linear in the block size and with modest table memory requirements. We also show that when such codes are used for mitigation of patterning effects in optical fibre communications, a gain of about 0.5 dB is possible under realistic conditions, at the expense of small redundancy (≈10%).

Multi-VPN Optimization for Scalable Routing via Relaying

Enterprise networks are increasingly adopting Layer-3 multiprotocol label switching (MPLS) virtual private network (VPN) technology to connect geographically disparate locations. The any-to-any direct connectivity model of this technology is causing routing tables in the service provider's routers to grow very large. The concept of relaying was proposed earlier to separately minimize the routing table memory footprint of individual VPNs by selecting a small number of hub routers to maintain complete reachability information for each VPN and enabling nonhub spoke routers with reduced routing tables to reach others by routing traffic via a hub. A large service provider network typically hosts thousands of different VPNs. In this paper, we generalize relaying to the multi-VPN environment and consider new constraints on resources shared across VPNs, such as router uplink bandwidth and memory. The hub selection problem involves complex tradeoffs along multiple dimensions including these shared resources and the additional distance traversed by traffic. We formulate the hub selection as a constraint optimization problem and develop an algorithm with provable guarantees to approximate this NP-complete problem. Evaluations using traces and configurations from a large provider indicate that the resulting relaying solution reduces the total router memory requirement by 85% while smoothing out the utilization on each router and requiring only a small increase in the end-to-end path for the relayed traffic.

A PSO based optimal switching technique for voltage harmonic reduction of multilevel inverter

Selected lower order harmonics of multilevel inverter are eliminated while the overall voltage THD is optimized by computing the switching angles using particle swarm optimization (PSO) technique. The discontinuity in the solution of selected harmonic elimination (SHE) problem at certain modulation indices is avoided by optimizing the individual harmonics to allowable limits. While choosing the set of solution leading to minimum THD, the abrupt changes in the switching angles are discarded by limiting the voltage THD within allowable limits. Also the selected higher order harmonics are eliminated by additional switching along with the lower order harmonics. In order to reduce the computational burden for online application, the switching angles computed by the proposed PSO technique for optimum THD at varying modulation indices are stored as a look-up table in the DSP memory. The simulated results are also validated through suitable experiments.

Modified Sliding-Block Distributed Arithmetic with Offset Binary Coding for Adaptive Filters

An efficient way for computing the response of an adaptive digital filter is to use sliding-block distributed arithmetic (SBDA). However, a disadvantage of distributed arithmetic is the amount of memory utilized. By encoding the memory tables in offset binary code (OBC), the size of the memory tables is reduced by half, while the computational workload remains unchanged. By modifying the computational flow, the computational workload can be reduced by almost by half at the expense of slightly more memory. This modified SBDA structure is called SBDA-OBC. It has memory requirements 25---50% lower than SBDA depending on the size of the sub-filter. In terms of the computational workload, SBDA-OBC is most advantageous for large sub-filters and when the filter is split into few sub-filters. In this case, the computational workload is reduced almost in half.

SpMT WaveCache: Exploiting Speculative Multithreading for Dataflow Computer

Speculative Multithreading(SpMT) increases the performance by means of executing multithreads speculatively to exploit thread-level parallelism. The authors expanded the transactional memory system of WaveCache by adding extra hardware components,such as Thread Synchronization Unit(TSU),Thread Context Table(TCT) and Thread Memory History(TMH),to improve the performance of SpMT WaveCache which is built on WaveScalar instruction set architecture(ISA). Furthermore,a novel two-levels commit method is proposed to support submitting thread-level transactions. Finally,the SpMT WaveCache is evaluated with 6 real benchmarks selected from SPEC,Mediabench and Mibench benchmarks. According to the experimental results,the SpMT WaveCache outperforms superscalar architecture ranging from 2X to 3X,and it also performs greater gain over original WaveCache and Transactional WaveCache. Therefore,the SpMT WaveCache is a good way to exploit thread-level parallelism of dynamic dataflow computer.

Adaptive Partial Response Maximum Likelihood Detection with Tilt Estimation Using Sync Pattern

We propose an improved detection method that concurrently adjusts the coefficients of equalizer and reference branch values in Viterbi detector. For the estimation of asymmetric channel characteristics, we exploit sync patterns in each data frame. Because of using the read-only memory (ROM) table to renew the coefficients of equalizer and reference values of branches, the complexity of the hardware is reduced. The proposed partial response maximum likelihood (PRML) detector has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with Hynix 0.35 µm standard cell library.

Partitioned Linear Interpolated Timing Recovery for Optical Discs

We have developed the partitioned linear interpolator for interpolated timing recovery (ITR), which provides the implementation of the ITR with a small memory table and the sufficient performance for optical discs.

A new model for distributed database systems - RETRACTED ARTICLE

A model is developed for allocating tables in a distributed database system. The model considers memory cost, transmission cost, table size and request rates, as well as updating rates of tables, the maximum allowable expected access times to tables at each computer and the memory capacity of each computer. The objective function is concerned with overall operating cost optimality. In this regard, the model is formulated as a non-linear integer zero–one programming problem, which can be converted into a linear zero–one programming model.

Nonlinearity correction for multibit /spl Delta//spl Sigma/ DACs

This paper presents a digital correction technique for wide-band multibit error-feedback (EF) digital-to-analog converters (DACs). The integral nonlinearity (INL) error of the multibit DAC is estimated (on line or off line) by a calibration analog-to-digital converter (CADC) and stored in a random-access memory table. The INL values are then used to compensate for the multibit DAC's distortion by a simple digital addition. The accuracy requirements for the error estimates are derived. These requirements can be significantly relaxed when the correction is combined with data-weighted averaging (DWA). Simulation and discrete-component measurement results are presented for a fourth-order 5-bit EF DAC. The results show a 14-bit DAC operating at an oversampling ratio of 8, which is suitable for digital subscriber line applications. The correction uses simple digital circuitry and a 3-bit CADC enhanced by DWA.

Mobile terminal operating in telephonic and tactile modes

In a mobile telephone terminal, a vibrator is provided for producing tactile sensation. In response to an input signal from a manual input device during a speech mode of communication, a vibrator-on signal is transmitted from the mobile telephone terminal to a mobile network. In response to the vibrator-on signal from the network, the vibrator is activated to produce tactile sensation. Preferably, a table memory is provided for mapping a number of signaling codes to a number of corresponding items of information. One of the signaling codes is selected in response to an input signal from the manual input device and the vibrator-on signal is transmitted to the network for indicating the selected signal code.