T-type Neutral Point Clamped Inverter Research Articles

Design of 3-Level T-type NPC Inverter for EV Applications

In recent years, there has been a significant demand for lightweight converters that provide exceptional control performance while generating minimal acoustic noise. This has resulted in higher switching signals for hard- switched 2-level low voltage 3-phase inverters. However, the increased switching frequencies have a negative impact on the inverters’ efficiency, requiring the use of expensive switch technology to maintain high efficiency. This paper aims to tackle these challenges by introducing the design and implementation of a extremely effective 3-Level T-Type Neutral Point Clamped (NPC) inverter designed for Electric Vehicle (EV) applications. 3-Level T-Type NPC inverter associates the strengths of both NPC and T-Type inverters. Similar towards the NPC, it offers a lower breakdown voltage for the switching devices, thereby reducing switching losses. Additionally, it shares the characteristics of the T-Type inverter, resulting in fewer conduction losses. To validate the feasibility of the converter, simulation is performed using MATLAB software, followed by the development and testing of a lab-scale prototype. The proposed three-level T-type NPC inverter have several merits over traditional 2-level inverters, including reduced distortion, switching losses, and improved efficiency. These benefits contribute to enhanced motor drive performance, reduced electromagnetic interference (EMI), and extended battery life in EVs.

Comparative evaluation of different DC-AC converter topologies for cryogenic applications utilizing superconducting materials

Modern transportation applications including electric vehicles (EVs), more electric aircraft (MEA) and electric comprise of different power conversion systems. Reduced weight and improved semiconductor efficiency are the major challenges towards their improved overall performance. To overcome them, cryogenic operation of power electronics converters (CPEC), electric motors, cables, and energy storage components has been under research and evaluation. CPEC are being investigated to drive superconducting machines (SCM) because of their lightweight structure and improved efficiency. CPEC can offer improved switching performance, reduced conduction losses and therefore increased efficiency; because of reduced on-resistance and increased carrier mobility of active devices. This article will discuss how can the benefits of lower operating temperature (< 93 K) be utilized in determining the most suitable DC-AC converter configuration. The paper compares three basic converter topologies: (a) two level voltage source inverter (2L-VSI), (b) three level t-type neutral point clamped inverter (3L-TNPC) and (c) two-level current source inverter (2L-CSI). Analysis is provided based on volume of passive components, electromagnetic interference (EMI) spectra and number of active devices, where all components considered are compatible with low temperatures. It can be observed that utilization of cryogenic temperature affects the volume of passive components, and therefore the overall selection of converter.

계통 연계형 3레벨 TNPC 인버터의 LVRT &amp; HVRT

With the increase in renewable power generation facilities, strict regulations on grid connection standards are being presented. The standards of Low Voltage Ride Through(LVRT) and High Voltage Ride Through(HVRT), which are representative grid connection standards to improve grid stability by maintaining grid connection in low and high voltage situations when a grid failure occurs, are gradually being subdivided. In this paper, the LVRT and HVRT control algorithms suggested in the transmission and distribution system connection regulations of KEPCO(Korea Electric Power Corporation) are applied to the grid-connected 3-level TNPC(T-Type Neutral Point Clamped) inverter. And in the VRT situation, the active and reactive current injection strategies were applied to the grid connected inverter algorithm. In addition, various simulation cases were analyzed, such as LVRT & HVRT conditions of transmission and distribution system. In the distribution system LVRT simulation, the grid voltage operated at 150ms and 1500ms, respectively, within 0.5p.u. and 0.75p.u. In the transmission system simulation, the LVRT operation and the HVRT operation were also simulated. By analyzing various simulation cases, the characteristics of the VRT cases was analyzed in detail and VRT control performance of the designed TNPC inverter was verified.

Performance Comparison Between Two-Level and Three-Level SiC-Based VFD Applications With Output Filters

One of the recent trends in power electronics field is to achieve high efficiency and compact size by using wide bandgap power devices such as silicon carbide (SiC) or gallium nitride switches. This paper compares the efficiency, the motor terminal voltage quality ( dv/dt ), and the common mode current of the SiC-based variable frequency drives (VFDs) according to the inverter topologies with and without the output filters. For this purpose, both the 2-level (2L) and 3-level (3L) topologies with SiC devices are built and tested. Here, the well-known 2L half-bridge inverter is compared with the well-known 3L T-type neutral point clamped inverter. A dv/dt filter and a sine wave filter have been discussed to satisfy the National Electrical Manufacturers Association standards as well. The experiments have been carried out with a 380-V/60-Hz, 3.7-kW induction motor and the custom designed power stages. Additionally, the experiments with both a 3-m and a 50-m cable length between the VFD and the induction motor are performed and reported.

Simplified model predictive control of a three‐phase T‐type NPC inverter

This study presents a simplified model predictive control (SMPC) strategy for three-phase T-type neutral-point-clamped (NPC) inverters to reduce the computational effort while achieving the current control, capacitor voltage equalisation and common-mode voltage (CMV) minimisation targets. The approach involves three stages. In the first stage, the number of switching states is reduced from 27 to 19 for reducing the peak CMV. In the second stage, a graphical approach is proposed to identify candidate control set (CCS) based on the present switching state, which helps in reducing the number of computations further. The number of elements in CCS may be 7, 10, 13 or 19. A look-up table with present applied state and its corresponding CCS is formed based on this graphical approach for all the 19 switching states. The third stage involves modifications to the MPC algorithm. Two versions of SMPC schemes (SMPC-I and SMPC-II) are proposed. SMPC-I can restrict the CMV to one-sixth of DC input voltage. SMPC-II can achieve near zero CMV. The performance of the SMPC strategy is analysed with parameter uncertainty. Computational effort of SMPC schemes is compared with other MPC methods. The feasibility of SMPC algorithm is verified experimentally on T-type NPC inverter prototype.

Hybrid PWM Strategy for Power Efficiency Improvement of 5-Level TNPC Inverter and Current Distortion Compensation Method

This paper proposes a pulse width modulation (PWM) strategy for improving the efficiency of a 5-level H-bridge T-type neutral point clamped (TNPC) inverter. In the case of the proposed PWM strategy, unlike the conventional PWM strategy in which both of the switching legs of the H-bridge inverter operate at a high frequency, one switching leg of the inverter operates at a low frequency. As the switching frequency is lowered, the switching loss is reduced, this improving the efficiency of the system. The duty references for the switching legs and the operating principle of the inverter are described in detail. The proposed PWM strategy, however, causes distortion of the output filter inductor current. The cause of the distortion has been analyzed and a compensation method is proposed to mitigate the distortion of the current. The effect of the proposed PWM strategy can be predicted through the loss calculation of the inverter for each modulation strategy. Furthermore, current distortion mitigation obtained by compensation method is confirmed through the simulation. In order to verify the effectiveness of the proposed strategy, a 2 kW H-bridge TNPC inverter prototype is implemented and tested. The simulation and experimental results show that the efficiency of the inverter is improved when the proposed PWM strategy is applied.

Model Predictive Current Control of a Three-Phase T-Type NPC Inverter to Reduce Common Mode Voltage

This paper presents a reduced control set model predictive control (RCSMPC) method for three-phase T-type neutral-point-clamped (NPC) inverter. The whole control set (WCS) consists of all the 27 switching states of T-type NPC inverter. The reduced control set (RCS) with 19 switching states is formed from WCS by excluding the switching states with common mode voltage (CMV) value higher than one-sixth of input DC voltage [Formula: see text]. With RCS, single-objective model predictive current control method can restrict the CMV peak value to [Formula: see text]. To further reduce the CMV below this threshold, a cost function with the weighted sum of two control targets is formulated in the RCSMPC method. The two control targets of RCSMPC method are CMV mitigation and load current control. The weight for CMV is called bias factor. The RCSMPC method is computationally efficient, as the number of switching states is less than that of WCSMPC. To further reduce the computational burden, CMV values corresponding to all the switching states are calculated offline and stored in memory. Robustness of both the methods is investigated with parameter deviations at different bias factors and reference currents. The proposed method is validated using simulation and experimental results and compared with the existing methods.

Design and Implementation of a Three-Phase Active T-Type NPC Inverter for Low-Voltage Microgrids

This paper presents the design and implementation of a 3 kVA three-phase active T-type neutral-point clamped (NPC) inverter with GaN power devices for low-voltage microgrids. The designed inverter is used in a battery-based energy system (BESS) for power conversion optimization in applications to low-voltage microgrids. A modular design method has been developed for the design and implementation of the AT-NPC inverter. Experimental verification has been carried out based on a 3-kW three-phase T-Type NPC grid-connected inverter. FPGA based digital control technique has been developed for the current control of the three-level three-phase grid inverter. A maximum efficiency of 98.49% has been achieved within a load range from 50% to 75%.

A Dual Three-Level T-NPC Inverter for High-Power Traction Applications

This paper proposes a dual three-level, T-type, neutral-point clamped (T-NPC) inverter fed dual permanent magnet synchronous motor topology for low-voltage, high-power traction applications. The switching pulses of the T-NPC inverters are interleaved and controlled, such that they produce equal and opposite three-phase currents at their output. This maintains balanced dc-link voltages in steady-state and transient conditions, even with slight mismatches between two sets of three-phase loads. Thus, the proposed configuration decouples the modulation strategy from the capacitor balancing control. Simulation and experimental results demonstrate that in comparison to the conventional single T-NPC inverter, the proposed topology reduces dc-link capacitors’ voltage deviation and current stress by more than 90% while avoiding additional switching instances to balance capacitor voltages.