Systolic Priority Queue Research Articles

Providing deterministic delay guarantees in ATM networks

B-ISDN is expected to carry various types of traffic for which stringent quality of service (QoS) requirements must be met. In particular, per-packet (per-cell) delay guarantees are an important QoS requirement for real-time applications. Although several methods have been proposed to provide delay guarantees in packet-switching networks, they are either too complex for ATM networks which allow only very simple operations to achieve high bandwidths (hence, high-speed switching and routing), or too inefficient (in using network resources) to be cost effective. In this paper, we propose a cell-multiplexing scheme for the real-time communication service in ATM networks. The proposed scheme achieves an efficiency close to that of packet-by-packet generalized processor sharing, and incurs an implementation cost similar to that of rate controlled static priority queueing. It employs the leaky bucket model as the input traffic description model and regulates the input traffic at the user network interface to follow the input traffic specification. Inside the network, it consists of two components, traffic controller and scheduler. The function of the traffic controller is to shape real-time traffic to have the same input pattern at every switch along the path. The end-to-end delay is bounded by the scheduler which employs a nonpreemptive rate-monotonic priority scheduling policy at each switch on the path. The proposed scheme is compared to three other popular schemes with MPEG-coded movie clips. Finally, we present a hardware implementation of the proposed scheme based on a systolic array priority queue.

An evaluation of the systolic stack sequential decoder

The performance of a sequential stack decoder based on a new systolic priority queue is evaluated using extensive simulations over both memoryless Gaussian channels and Rayleigh fading channels. The results are used to determine interrelations between the decoder parameters, providing a simple way to design a systolic stack sequential decoder with an overall erasure probability approximately equal to the probability of a correct path overflow, while keeping the bit error rate of the decoder almost as low as that of the code. It is shown that this decoder circumvents some of the limitations inherent to usual stack decoders, while offering an increased decoding speed and being well suited for vlsi implementation.

Multiple-inputs systolic priority queue for fast sequential decoding of convolutional codes

The operating speed of a sequential decoder with stack algorithm is usually limited by the time to search the best node for further extension. This problem can be completely alleviated by using the systolic priority queue to replace the stack memory. However, the systolic priority queues developed previously are accessible only in the cases when the number of inputs processed is small. This is because the complexity of a queue grows up quickly as the volume of data flowing through it increases. Since the largest amount of data flowing through a systolic priority queue is equal to the number of inputs to this queue, the systolic priority queue is not suitable for a system with many inputs. A modified version of previously developed circuits is proposed. The number of transmission gates required in this circuit is proportional to 3N instead of N/sup 2/, where N is the number of inputs. Also the total number of control signals is proportional to 3N/sup 2/ instead of N/sup 3/. But the number of comparators required is proportional to C/sub 2//sup N+1/, as before. This modified circuit can be used in cases where the number of inputs is small (N/spl les/8). A new algorithm for the multiple-inputs systolic priority queue (MISPQ) is proposed. By using this algorithm, a MISPQ may be implemented with several smaller queues, each is used to process a part of data in the MISPQ. Since the volume of data flowing through each queue is small, these queues will be simpler. However, some additional circuits should be used for the interactions between queues. A circuit for implementing this algorithm is presented and its complexity is analysed. The number of transmission gates for the MISPQ is proportional to 3N, the number of control signals is proportional to (3N/sup 2//2), and the number of comparators is proportional to 4C/sub 2//sup N/2+1/. Thus this new architecture is feasible for large N (e.g.N/spl ges/8).

A systolic architecture for fast stack sequential decoders

The troublesome operation of reordering the stack in stack sequential decoders is alleviated by storing the nodes in a systolic priority queue that delivers the true top node in a short and constant amount of time. A new systolic priority queue is described that allows each decoding step, including retrieval, reordering and storage of the nodes, to take place in a single clock period. A complete decoder architecture designed around this queue is compared to a conventional stack-bucket architecture from both speed and cost points of view. The proposed decoder architecture appears to be faster, affordable, and compatible with convolutional codes having long memory and high coding rate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Sequential decoding of convolutional codes by a compressed multiple queue algorithm

The conventional multiple stack algorithm (MSA) is an-efficient approach for solving erasure problems in sequential decoding. However, the requirements of multiple stacks and large memory make its implementation difficult. Furthermore,the MSA allows only one stack to be in use at a time: the ether stacks will stay idle until the process in that stack is terminated. Thus it seems difficult to implement the MSA with parallel processing technology. A two-stack scheme is proposed to achieve similar effects to the MSA. The scheme greatly reduces the loading for data transfer and I/O complexity required in the MSA, and makes parallel processing possible. An erasure-free sequential decoding algorithm for convolutional codes, the compressed multiple-queue algorithm (CMQA), is introduced, based on systolic priority queue technology, which-can reorder the path metrics in a short and constant time. The decoding speed will therefore be much faster than in traditional sequential decoders using sorting methods. In the CMQA, a systolic priority queue is divided into two queues by adding control signals, thereby simplifying implementation. Computer simulations show that the CMQA outperforms the MSA in bit error rate, with about one-third the memory requirement of the MSA.

SYSTOLIC ARRAY PROCESSING OF THE SEQUENTIAL DECODING ALGORITHM

A systolic array processing technique is applied to implementing the stack algorithm form of the sequential decoding algorithm. It is shown that sorting, a key function in the stack algorithm, can be efficiently realized by a special type of systolic arrays known as systolic priority queues. Compared to the stack-bucket algorithm, this approach is shown to have the advantages that the decoding always moves along the optimal path, that it has a fast and constant decoding speed and that its simple and regular hardware architecture is suitable for VLSI implementation. Three types of systolic priority queues are discussed: random access scheme, shift register scheme and ripple register scheme. The property of the entries stored in the systolic priority queue is also investigated. The results are applicable to many other basic sorting type problems.

A Systolic Design for Connectivity Problems

In this paper we present a design, suited to VLSI implementation, for a one-dimensional array to solve graph connectivity problems. The computational model is relatively primitive in that only the two end cells of the array can interact with the external environment and only adjacent cells in the array are allowed to communicate. However, we show that an array of n + 1 cells can be used for a graph with n vertices to find the connected components, a spanning tree, or, when used in conjunction with a systolic priority queue, a minimum spanning tree. The area, time, and I/O requirements compare favorably with other models proposed for this problem in the case of sparse graphs.