Systematic Jitter Research Articles

A 1.12–1.91 mW/GHz 2.46–4.92 GHz Cascaded Clock Multiplier in 65 nm CMOS

We present a low-power and low jitter two-stage 2.46&#x2013;4.92-GHz clock multiplier using a 38.4-MHz reference clock. The proposed clock multiplier implements an <inline-formula> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> clock multiplication with a delay-locked loop and an edge combiner (EC) in the first stage. The regulated supply of the voltage-controlled delay line and EC within the delay-locked loop limits the first-stage clock multiplication voltage sensitivity. An in-depth phase noise analysis of the first stage with the proposed phase domain modeling and spur analysis in the EC helps low-power clock multiplier design. The first-stage output injection locks a pseudo-differential ring oscillator embedded in a frequency tracking loop, thereby achieving a <inline-formula> <tex-math notation="LaTeX">$64\times $ </tex-math></inline-formula>&#x2013;<inline-formula> <tex-math notation="LaTeX">$128\times $ </tex-math></inline-formula> clock multiplication in the second stage. In collaboration with the simulated phase noise from sources, a system-level phase noise modeling defines the design specifications of the two stages for minimum output jitter in a given power budget. Fabricated in a 65-nm CMOS process, the first-stage clock multiplier achieves an integrated jitter 761 fs_rms at 307.2 MHz while consuming 2.5 mW. The mismatch and offset-induced systematic jitter is calibrated, giving &#x2212;53.4-dBc reference spur at the first-stage output. The second-stage injection-locked clock multiplier adds low random jitter to the first stage with total output jitter 825 fs_rms at 4.92 GHz, &#x2212;28.2-dBc reference spur, and 3-mW power consumption.

The Magnitude of the Frequency Jitter of Acoustic Waves Generated by Wind Instruments Is of Relevance for the Live Performance of Music

It is shown that a gold-plated device mounted on a tenor saxophone, forming a small bridge between the mouthpiece and the S-bow, can change two characteristics of the radiated sound: (1) the radiated acoustic energy of the harmonics with emission maxima around 1500–3000 Hz, which is slightly reduced for tones played in the lower register of the saxophone; (2) the frequency jitter of all tones in the regular and upper register of the saxophone show a two-fold increase. Through simulated phase-shifted superimpositions of the recorded waves, it is shown that the cancellation of acoustic energy due to antiphase superimposition is significantly reduced in recordings with the bridge. Simulations with artificially generated acoustic waves confirm that acoustic waves with a certain systematic jitter show less cancelling of the acoustic energy under a phase-shifted superimposition, compared to acoustic waves with no frequency jitter; thus, being beneficial for live performances in small halls with minimal acoustic optimization. The data further indicate that the occasionally hearable “rumble” of a wind instrument orchestra with instruments showing slight differences in the frequency of the harmonics might be reduced (or avoided), if the radiated acoustic waves have a systematic jitter of a certain magnitude.

Jitter Remains Stable Throughout a Single Fiber EMG Session in Healthy and Myasthenic Muscles.

Fatigability is the hallmark of myasthenia gravis (MG). It is not clear, however, whether there is an analogous increase in jitter during the course of a single fiber electromyography (SFEMG) session. The individual jitter values of all potentials of 76 normal and 44 myasthenic orbicularis oculi muscles were assigned a rank number according to their temporal order in which they were collected and linear regression was performed to determine if the slope of the regression line was significantly different from zero. Control and MG subjects displayed rather flat linear regression lines with non-significant positive or negative slopes. Accordingly, ROC analysis yielded areas under the curve near 0.5. We conclude that there is no systematic jitter increase during the collection of 20 potential pairs in a typical SFEMG session.

A low-jitter leakage-free digitally calibrated phase locked loop

A digital calibration scheme is proposed to reduce the systematic jitter due to the periodic current leakage in charge pump phase-locked loops. Frequency acquisition is performed through a feed-forward digitally assisted path. Then, the calibration loop digitally accomplishes the phase adjustment. Lock time is improved by applying the dynamic control on loop gain during the frequency acquisition. Using 32 overshoots/undershoots for calibration, peak-to-peak and root-mean-square jitter are reduced to 1.78pS and 0.57pS at 1.6 GHz operating frequency, when 1.8 V supply is subject to 80 mV random noise. Phase noise at 1 GHz reference frequency achieves to −117dBc/Hz and −120dBc/Hz, at 1MHz offset frequency, when the calibration is accomplished for N = 16 and N = 32, respectively. All the design is implemented in a 0.15 mm2 area, and consumes 3.35 mW power at 1.8 V supply. Post-Layout simulation results are presented using the Berkeley short-channel insulated-gate field-effect transistor model, version3, in a 0.18 µm technology.

A fast-locking low-jitter digitally-enhanced DLL dynamically controlled for loop-gain and stability

Conventional structure of delay locked loops (DLLs) is modified to achieve better jitter and smaller lock time. In the proposed structure, analog charge pump is eliminated, to remove the problems of leakage current on output capacitance, and is replaced by combination of a digital accumulator (ACC) and a digital-to-analog converter. A programmable ACC is also proposed, to dynamically control the loop gain and lock time. When the loop enters to lock region at the first time, a lock detector block disables ACC and equivalent digital code is stored on a latch array. So, a fixed control voltage controls delay elements and the systematic jitter, due to periodic discharge of control voltage. RMS jitter of less than 33.5 and 1.6 ps are achieved at 20 and 625 MHz operating frequencies, respectively, when the supply is subject to 110 mV random noise and also 40 mV periodic noise, related to generated clock signals. Lock time is reduced from 38 to 2 µs at 20 MHz, and also from 900 to 45 ns at 600 MHz, when the proposed dynamic control mechanism is applied on the loop. Total power consumption for the main core of DLL is 7.85 mW at 1.8 V supply in 0.18 µm CMOS process.

Technique to Reduce the Resolution Requirement of Digitally Controlled Oscillators for Digital PLLs

Phase-locked loops (PLLs) are a critical component in modern systems. Digital PLLs (DPLLs) are increasingly popular in CMOS technologies due to their ease of integration and scalability with digital logic. However, digital quantization results in larger steady-state systematic jitter, or dithering. High resolution is needed to control the oscillator to minimize the dithering. This brief proposes a simple method to reduce the frequency-resolution requirement. The method allows for substantial reduction in the hardware complexity without sacrificing the DPLL's dynamic characteristics

Theoretical characterisation and practical implementation of optical fibre PPM self synchronisation sequences

AbstractA novel technique for estimating the optical fibre PPM frame phase and eliminating the pattern dependent jitter is proposed while practical implementations and a mathematical characterisation for the technique are reported. Use is made of naturally occurring sequences thus avoiding the sensitivity and bit rate penalties associated with the previous methods. Tracking additional sequences is demonstrated and shown to be beneficial resulting in a frame rate discrete component enhancement of 10.8 dB and timing variance reduction from 12 × 10−3 rad2 to 3.6 × 10−3 rod2. Utilising the systematic jitter rejection method proposed resulted in a measured timing variance reduction from 3.6 × 10−3 rad2 to 4.2 × 10−5 rod2. The limit is imposed by the PLL performance while good correlation is depicted with the theoretical model.

Frame Synchronisation for Overlapping Optical Fiber PPM with Systematic Jitter Rejection

Frame Synchronisation for Overlapping Optical Fiber PPM with Systematic Jitter Rejection

Jitter accumulation in a simulated 591.2 Mbit/s, 6000 km optical transmission system

An equivalent-time jitter synthesis experiment is described which allows laboratory evaluation of transoceanic regenerated optical transmission systems. Results are reported for the systematic timing jitter accumulation obtained over a 591.2 Mbit/s, 6000 km route derived from the simulated concatenation of 60 regenerated sections.

Jitter in digital networks

The accumulation and tolerance of timing jitter in digital networks is analysed for transmission links containing regenerators as well as dejitterizers and/or multiplexer—demultiplexer pairs, and for timing circuits employing phase-locked-loops. Both systematic pattern-dependent jitter and waiting-time jitter are taken into account. It is shown that, under practical circumstances, the total accumulated jitter can be adequately described by some simple equations and measurement data confirm these equations. An experimental relation between peak-peak jitter values over a long period and those over a short period is presented. The results of the analysis have led to the conclusion that the internationally recommended maximum permissible peak-peak jitter values at digital interfaces will never be reached in the Dutch digital network.

Jitter Accumulation for Periodic Pattern Signals

It is important to accurately evaluate and reduce jitter accumulation in long-haul digital repeatered lines. Jitter accumulation caused by random pattern signals has already been analyzed. However, periodic pattern signals such as pseudorandom signals are usually used to measure jitter accumulation. This paper describes the difference between the jitter accumulation for both signals and the necessary conditions to accurately estimate jitter accumulation for random pattern signals by using periodic pattern signals. First, it is shown theoretically that systematic jitter for periodic signals saturates, showing a ripple pattern. The limit of increase is determined by the ratio of tank bandwidth and pattern repetition frequency. Up to a certain number of regenerators determined by the ratio, systematic jitter increases in rough proportion to the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\sqrt{N}</tex> slope. It is also shown that the equation to estimate random pattern jitter accumulation is determined by the measured value for periodic pattern signals. Second, jitter characteristics are simulated by optical signal circulating experiments. The results are in agreement with the analysis. In addition, the reduction effects on periodic signal jitter accumulation caused by timing signal delay and nonlinearity of the limiter in the timing circuit are shown.

Jitter accumulation in optical transmission systems

Jitter accumulation on a high-bit-rate submarine optical link has been investigated through signal circulating experiments. One-, 6- and 12-repeater loops exhibit similar accumulation. The variance of the systematic jitter increases as the number of repeaters and the random jitter tends to saturate.

Systematic jitter suppression by pattern inversion

A jitter suppression method using simple pattern inversion at each regenerator is proposed. It is theoretically shown that this method is very effective for systematic jitter suppression. The results of a signal circulating experiment using a 446 Mbit/s optical regenerator agree with the theoretical estimation.

Analysis of Jitter Peaking Effects in Digital Long-Haul Transmission Systems Using SAW-Filter Retiming

The new lightwave long-haul transmission systems typically use surface-acoustic-wave (SAW) filters for timing recovery, in place of the phase-locked loops favored in slower systems. We report here analytical studies of phenomena allowed by two kinds of filter ripple. The ripple is capable of causing to accumulate exponentially with the number of regenerators N in a repeatered line. Such behavior is well known in the case of phase-locked-loop retiming, where the jitter peaking that usually appears in the loop response must be carefully limited to avoid exponential growth. We show that equivalent phenomena can appear when the SAW filters exhibit passband ripple, or, as previously reported in condensed form, When ripple-free filters are detuned by approximately one-half the full 3 dB bandwidth. Furthermore, in the case of ripply filters, exponential accumulation is found to be much more pronounced for random than for systematic jitter. In addition, the alignment within each regenerator can grow exponentially along the chain of regenerators. Neither of these statements is true in the case of the ripple-free filters previously treated in the literature.

Accumulation of Jitter: A Stochastic Model

A problem that has been considered extensively in the past is the accumulation of jitter in a chain of regenerative repeaters. For simplicity it is usually assumed that all repeaters in the chain are identical. However, this is not the case in real systems, where considerable differences among the repeaters of a chain have been observed. These random variations are due mainly to manufacturing tolerances, aging effects, temperature changes, etc. In this work, we examine the accumulation of systematic and random jitter along the chain, when the repeater transfer functions are subjected to random variations. We derive expressions for the expected value and variance of the output jitter spectrum in terms of average values of the repeater's jitter transfer function. In addition we find the expected value and the variance of the RMS jitter. Finally we examine two special cases where the timing circuit employs either a phased-locked loop or a surface acoustic wave filter, and derive some asymptotic relations for the power spectral density and root-mean-square value of the accumulated systematic jitter.

Jitter accumulation with SAW timing extraction at 325 Mbaud

Random, systematic and alignment jitter accumulation on a cascade of 10×325 Mbaud regenerators using SAW timing extraction is described. Good agreement between measurement and theory is shown in each case and a significant advantage over RLC extraction demonstrated.

Tolerable Q-Factor Variations in PCM Lines

This paper makes a theoretical assessment of the performance impairments that may be caused on PCM lines by the use of different timing extraction bandwidths in tandem. Two basic situations are examined: 1) random transmitted pattern, and 2) transition between two repetitive patterns. In both cases, the analysis of jitter propagation and acceptance indicates that there is a limited degree of bandwidth inconsistency that may be tolerated. The amount of tolerable inconsistency is derived in both cases, according to different criteria that are established for convenience in each case. The effect of systematic line jitter on the correlation between a repeater performance in the field and in bench tests is also discussed. The study is based on a well-known model of jitter propagation introduced by Byrne et al. [1]. The general conclusion of the paper is that Q -factor variations in a PCM line should be kept lower than a factor of two in order to avoid errors during pattern transitions and lower than 1.5 in order to avoid noise immunity loss.

Time jitter in self-timed regenerative repeaters with correlated transmitted symbols

This paper deals with the calculation of systematic time jitter in a self-timed regenerative repeater, where the timing circuit consists of a square-law device followed by a high-Q resonant circuit tuned to the transmission rate and a down zero-crossing detector. The method presented here can be used for any linecoding scheme and waveshape of finite duration. Some interrelations between the selected line code and waveform are also studied for the given timing recovery circuit. Examples for different waveforms and codes of practical importance are presented.

An Analysis of Jitter Accumulation in a Chain of PLL Timing Recovery Circuits

This paper analyzes the timing jitter accumulation which is produced in a chain of regenerative repeaters when a second-order phase-locked loop (PLL) is used as a timing filter. In a PLL timing recovery circuit, the growth of timing jitter varies with the value of damping factor \zeta . In this paper, therefore, approximate equations of timing jitter accumulation are given with respect to a case in which \zeta is sufficiently large, and the timing jitter is calculated with a digital computer for various values of \zeta . It is shown that, when \zeta is sufficiently large, results similar to those for first order loops or single tuned circuits are obtained, i.e., the meansquare random jitter is almost proportional to the square root of the number of repeaters, and the mean-square systematic jitter is almost proportional to the number of repeaters. When \zeta is small the meansquare jitter increases exponentially as the number of repeaters is increased. This paper also describes the optimum value of \zeta , considering both the jitter accumulation and the transient response of the PLL, by using the number of repeaters N as a parameter. As a result, it is postulated that the optimum value of \zeta is 5 to 8 when N is 100, and 15 to 18 when N is 1,000.

PCM Jitter Suppression by Scrambling

Jitter suppression in a chain of baseband PCM repeaters is studied. It is shown that a scrambler is very effective for systematic jitter suppression and that beyond 5 stages little additional suppression results. The probability of mark in the scrambler output converges to 0.5, independently of that in the input PCM signal. Experimental results confirm the analysis and show the ability of the scrambler to reduce the systematic jitter. The timing information disappearance of PCM repeatered lines when the scrambler is applied is also discussed.