PSoC Research Articles

Ses Efektlerine Özel Yüksek Seviye Hızlandırıcılarla Düşük Gecikmeli SoC Tasarımı

High-quality sound processing requires hardware acceleration in order to reduce the processing latency of the applied effect over the sound. Computational latency of creating enhanced sound from the audio input is an important delay component and affects the performance especially in artists’ live performance or high-quality sound generation. Artists want to apply a sound effect on their music and latency is the main problem when these systems running in real-time. CPU-based systems present flexibility, but introduce a high amount of latency while processing, which in fact affects the artist negatively. In this study, to get the flexibility through software and the acceleration via hardware specialization, we present a system-on-chip (SoC) solution with HW/SW co-design methodology for sound-effects. We reduce the latency and increase the frequency by applying pipelining through MATLAB. The system is implemented and tested on programmable SoC platform, ZedBoard, which contains ZC7020 Zynq chip with a dual-core ARM-Cortex-A9 processor. The ARM processor enables the management of sound-effect hardware accelerator running on FPGA and communication with user. Sound effect is designed with block models provided by MATLAB & Simulink. HDL Coder converts these blocks into RTL-level hardware designs. The followed design methodology provided by MATLAB & Simulink enables high-level block design that can be embedded into FPGA at RTL-level to benefit from the speed provided by high-speed hardware registers and to have an AXI interconnect interfacing with software in order to utilize the software flexibility. The study shows that latency is reduced significantly.

Deep reinforcement learning‐based autonomous parking design with neural network compute accelerators

AbstractWe describe the design and implementation of an autonomous prototype vehicle which finds an empty parking slot in a parking area, and parks itself in the empty parking slot, using neural networks based on deep reinforcement learning (RL). To perform an autonomous parking procedure for our prototype vehicle, two different artificial neural networks (ANNs) are trained using a deep RL Algorithm in a simulation environment and embedded into the computing platform of the prototype car. One of the ANNs enables the vehicle to drive autonomously in the parking environment. At the same time, an image processing algorithm is used to determine whether a parking slot is empty. When the image processing algorithm finds a suitable parking slot, a different ANN is activated and performs a safe parking procedure. However, ANN‐based machine learning techniques require high processing power and impose a high computational burden on embedded CPU and GPU platforms. To alleviate the computational burden, one can achieve higher performance and less power consumption using an application‐specific hardware design, where logic resources are fully exploited according to the algorithm of interest, in an energy‐efficient manner. In this article, hardware accelerators for our ANN models are designed and generated via the Vivado high‐level synthesis (HLS) tool, targeting an ARM based programmable SoC platform, ZedBoard. Our ANN accelerators have achieved a speedup of 17x as compared to an ARM software implementation. For deeper fully‐connected layers used in deep RL‐based solutions, function‐level parallelism (Vivado's dataflow) is employed to improve the computational efficiency. Our proposed stage‐level description for fully connected layers outperforms recent studies in terms of computation time.

Remote Laboratory for E-Learning of Systems on Chip and Their Applications to Nuclear and Scientific Instrumentation

Configuring and setting up a remote access laboratory for an advanced online school on fully programmable System-on-Chip (SoC) proved to be an outstanding challenge. The school, jointly organized by the International Centre for Theoretical Physics (ICTP) and the International Atomic Energy Agency (IAEA), focused on SoC and its applications to nuclear and scientific instrumentation and was mainly addressed to physicists, computer scientists and engineers from developing countries. The use of e-learning tools, which some of them adopted and others developed, allowed the school participants to directly access both integrated development environment software and programmable SoC platforms. This facilitated the follow-up of all proposed exercises and the final project. During the four weeks of the training activity, we faced and overcame different technology and communication challenges, whose solutions we describe in detail together with dedicated tools and design methodology. We finally present a summary of the gained experience and an assessment of the results we achieved, addressed to those who foresee to organize similar initiatives using e-learning for advanced training with remote access to SoC platforms.

IDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing.

In recent years, there has been an increasing demand to digitize and electronically access historical records. Optical character recognition (OCR) is typically applied to scanned historical archives to transcribe them from document images into machine-readable texts. Many libraries offer special stationary equipment for scanning historical documents. However, to digitize these records without removing them from where they are archived, portable devices that combine scanning and OCR capabilities are required. An existing end-to-end OCR software called anyOCR achieves high recognition accuracy for historical documents. However, it is unsuitable for portable devices, as it exhibits high computational complexity resulting in long runtime and high power consumption. Therefore, we have designed and implemented a configurable hardware-software programmable SoC called iDocChip that makes use of anyOCR techniques to achieve high accuracy. As a low-power and energy-efficient system with real-time capabilities, the iDocChip delivers the required portability. In this paper, we present the hybrid CPU-FPGA architecture of iDocChip along with the optimized software implementations of the anyOCR. We demonstrate our results on multiple platforms with respect to runtime and power consumption. The iDocChip system outperforms the existing anyOCR by while achieving higher energy efficiency and a increase in recognition accuracy.

Design and Implementation of Embedded Real-Time English Speech Recognition System Based on Big Data Analysis

This article uses Field Programmable Gate Array (FPGA) as a carrier and uses IP core to form a System on Programmable Chip (SOPC) English speech recognition system. The SOPC system uses a modular hardware system design method. Except for the independent development of the hardware acceleration module and its control module, the other modules are implemented by software or IP provided by Xilinx development tools. Hardware acceleration IP adopts a top-down design method, provides parallel operation of multiple operation components, and uses pipeline technology, which speeds up data operation, so that only one operation cycle is required to obtain an operation result. In terms of recognition algorithm, a more effective training algorithm is proposed, Genetic Continuous Hidden Markov Model (GA_CHMM), which uses genetic algorithm to directly train CHMM model. It is to find the optimal model by encoding the parameter values of the CHMM and performing operations such as selection, crossover, and mutation according to the fitness function. The optimal parameter value after decoding corresponds to the CHMM model, and then the English speech recognition is performed through the CHMM algorithm. This algorithm can save a lot of training time, thereby improving the recognition rate and speed. This paper studies the optimization of embedded system software. By studying the fixed-point software algorithm and the optimization of system storage space, the real-time response speed of the system has been reduced from about 10 seconds to an average of 220 milliseconds. Through the optimization of the CHMM algorithm, the real-time performance of the system is improved again, and the average time to complete the recognition is significantly shortened. At the same time, the system can achieve a recognition rate of over 90% when the English speech vocabulary is less than 200.

Phased-array antennas using novel PSoC-controlled phase shifters for wireless applications

AbstractThe paper proposes a system consisting of novel programmable system on chip (PSoC)-controlled phase shifters which in turn guides the beam of an antenna array attached to it. Four antennae forming an array receive individual inputs from the programmable phase shifters (IC 2484). The input to the PSoC-based phase shifter is provided from an optimized 1:4 Wilkinson power divider. The antenna consists of an inverted L-shaped dipole on the front and two mirrored inverted L-shaped dipoles mounted on a rectangular conductive structure on the back which resonates in the ISM/Wi-Fi band (2.40–2.48 GHz). The power divider is designed to provide the feed to the phase shifter using a beamforming network while ensuring good isolation among the ports. The power divider has measured S11, S21, S31, S41, and S51 to be −14, −6.25, −6.31, −6.28, and −6.31 dB, respectively at a frequency of 2.45 GHz. The ingenious controller is designed in-house using a PSoC microcontroller to regulate the control voltage of individual phase shifter IC and generate progressive phase shifts. To validate the calibration of the in-house designed control circuit, the phased array is simulated using $s_p^2$ touchstone file of IC 2484. This designed control circuit exhibits low insertion loss close to −8.5 dB, voltage standing wave ratio of 1.58:1, and reflection coefficient (S11) is −14.36 dB at 2.45 GHz. Low insertion loss variations confirm that the phased-array antenna gives equal amplitude and phase. The beamforming radiation patterns for different scan angles (30, 60, and 90°) for experimental and simulated phased-array antenna are matched accurately showing the accuracy of the control circuit designed. The average experimental and simulated gain is 13.03 and 13.48 dBi respectively. The in-house designed controller overcomes the primary limitations associated with the present electromechanical phased array such as cost weight, size, power consumption, and complexity in design which limits the use of a phased array to military applications only. The current study with novel design and enhanced performance makes the system worthy of the practical use of phased-array antennas for common society at large.

A Study of Programmable System on Chip (PSoC) Technology for Engineering Education

This paper obtain the introducing of Programmable System on Chip (PSoC) technology for Engineering Education, consisting of 2 types of PSoC, i.e, CyPress Semiconductor CY8CKIT-049-42xx, and PSoC 6 Bluetooth Low Energy (BLE), in this paper it focuses on learning at the level basic and introduction to these 2 types of PSoC. moreover, Learning consists of introducing the PSoC input-output with a block diagram of a typical MCU, PSoC Creator features, installation, and testing using Light Emitting Diode (LED). It is hoped that students in the engineering field can understand PSoC as one of the competing microcontrollers of the Arduino or ATmega328p, therefore, that obtains the gain knowledge about the MCU extensively.

Analog Considerations for Designing a Potentiostat in a PSoC: Sources of Errors and Compensation Techniques

Designing with a Programmable System on a Chip (PSoC) allows for entire circuit designs to be implemented with a single commercially available chip and eliminates the need to physically assemble electronic components. This is possible as the PSoC incorporates a microcontroller with digital and analog components into a single package. While this design allows for much easier implementation of circuits, there are some drawbacks. In this paper we will demonstrate one of those drawbacks, high routing resistance in parts of the analog mesh that connects the analog parts and external pins. We show how this resistance can cause measurement errors when the PSoC is implemented as a single chip potentiostat. As the internal analog routing resistance is in the kΩ range, measuring currents in the Kॅ range can cause mV errors, leading to lose of voltage control during electrochemical experiments. We also demonstrate a calibration routine to compensate for this voltage error that reduced the error by over 90%.

Retracted] Design and Implementation of SOC‐Based Noncontact‐Type Level Sensing for Conductive and Nonconductive Liquids

In contrast to the existing electromechanical systems, the noncontact‐type capacitive measurement allows for a chemically and mechanically isolated, continuous, and inherently wear‐free measurement. Integration of the sensor directly into the container’s wall offers considerable savings potential because of miniaturization and installation efforts. This paper presents the implementation of noncontact (NC)‐type level sensing techniques utilizing the Programmable System on Chip (PSoC). The hardware system developed based on the PSoC microcontroller is interfaced with capacitive‐based printed circuit board (PCB) strip. The designer has the choice of placing the sensors directly on the container or close to it. This sensor technology can measure both the conductive and nonconductive liquids with equal accuracy.

Kontroler ruke industrijskog robota baziran na programabilnom SoC uređaju

Field-programmable gate arrays (FPGAs) and, recently, System on Chip (SoC) devices have been applied in a wide area of applications due to their flexibility for real-time implementations, increasing the processing capability on hardware as well as the speed of processing information in real-time. The most important applications based on FPGA/SoC devices are focused on signal/image processing, Internet of Things (IoT) technology, artificial intelligence (AI) algorithms, energy systems applications, automatic control and industrial applications. This paper develops a robot arm controller based on a programmable System-OnChip (SoC) device that combines the high-performance and flexibility of a CPU and the processing power of an FPGA. The CPU consists of a dual-core ARM processor that handles algorithm calculations, motion planning and manages communication and data manipulation. FPGA is mainly used to generate signals to control servo and read the feedback signals from encoders. Data from the ARM processor is transferred to the programmable logic side via the AXI protocol. This combination delivers superior parallel-processing and computing power, real-time performance and versatile connectivity. Additionally, having the complete controller on a single chip allows the hardware design to be simpler, more reliable, and less expensive.

Fault Injection on a Mixed-Signal Programmable SoC with Design Diversity Mitigation

This paper presents an approach for runtime software-based fault injection, applied to a commercial mixed-signal programmable system-on-chip (PSoC). The fault-injection scheme is based on a pseudo-random sequence generator and software interruption. A fault tolerant data acquisition system, based on a design diversity redundant scheme, is considered as case study. The fault injection is performed by intensively inserting bit flips in the peripherals control registers of the mixed-signal PSoC blocks, as well as in the SRAM memory of the device. Results allow to evaluate the applied fault tolerance technique, indicating that the system is able to tolerate most of the generated errors. Additionally, a high fault masking effect is observed, and different criticality levels are observed for faults injected into the SRAM memory and in the peripherals control registers.

An Intelligent System-on-a-Chip for a Real-Time Assessment of Fuel Consumption to Promote Eco-Driving

Pollution that originates from automobiles is a concern in the current world, not only because of global warming, but also due to the harmful effects on people’s health and lives. Despite regulations on exhaust gas emissions being applied, minimizing unsuitable driving habits that cause elevated fuel consumption and emissions would achieve further reductions. For that reason, this work proposes a self-organized map (SOM)-based intelligent system in order to provide drivers with eco-driving-intended driving style (DS) recommendations. The development of the DS advisor uses driving data from the Uyanik instrumented car. The system classifies drivers regarding the underlying causes of non-optimal DSs from the eco-driving viewpoint. When compared with other solutions, the main advantage of this approach is the personalization of the recommendations that are provided to motorists, comprising the handling of the pedals and the gearbox, with potential improvements in both fuel consumption and emissions ranging from the 9.5% to the 31.5%, or even higher for drivers that are strongly engaged with the system. It was successfully implemented using a field-programmable gate array (FPGA) device of the Xilinx ZynQ programmable system-on-a-chip (PSoC) family. This SOM-based system allows for real-time implementation, state-of-the-art timing performances, and low power consumption, which are suitable for developing advanced driving assistance systems (ADASs).

Differential Pressure Transmitter With Unified Electronics Unit

Differential pressure is an important technological parameter. To date, the lion's share of research in this area has focused on the development and improvement of differential pressure transmitters. This article is devoted to developing a differential pressure transmitter with unified electronics unit. To achieve this objective, modern methods and technologies were used in the development of the electronics unit of the pressure transmitter. The Programmable System-on-Chip (PSoC) technology was used to develop the electronics unit. Due to the use of PSoC technology, it was possible to increase the noise immunity of the developed differential pressure transmitter, as well as provide an unparalleled combination of flexibility, integration analog and digital functionality. The operational principle of the developed differential pressure transmitter is based on the dependence of the elastic deformation of the sensitive element of the transmitter on the pressure. A strain gauge and a differential capacitive sensor were considered as sensitive elements of the proposed differential pressure transmitter.

A Programmable SoC Based Accelerator for Privacy Enhancing Technologies and Functional Encryption

A Programmable SoC Based Accelerator for Privacy Enhancing Technologies and Functional Encryption

Lightweight and Energy-Efficient Implementation of an Unclonable WSN Nodes on PSoC

An adversary can easily capture a wireless sensor network (WSN) node and extract the security information stored in the node, including keys, shared secrets and so on. Due the resources limitation, the traditional encryption and authentication protocols are impractical on WSN nodes. In this letter, we proposed a lightweight and energy-efficient anti-clone design for the WSN nodes, in which physical unclonable function (PUF) is adopted to enhance the security of the WSN nodes. The new structure aims at achieving a low cost and low energy method to prevent the node to be captured and cloned by the adversary. Unclonable WSN nodes are implemented on cypress PSOC 4, in which a configurable PUF structure is accomplished by use the universal digital block. Experimental results show that the proposed system can prevent the capture and clone attack in wireless sensor network, which is unavailable in previous WSN nodes.

A Programmable SoC-Based Accelerator for Privacy-Enhancing Technologies and Functional Encryption

A multitude of privacy-enhancing technologies (PETs) has been presented recently to solve the privacy problems of contemporary services utilizing cloud computing. Many of them are based on additively homomorphic encryption (AHE) that allows the computation of additions on encrypted data. The main technical obstacles for adaptation of PETs in practical systems are related to performance overheads compared with current privacy-violating alternatives. In this article, we present a hardware/software (HW/SW) codesign for programmable systems-on-chip (SoCs) that is designed for accelerating applications based on the Paillier encryption. Our implementation is a microcode-based multicore architecture that is suitable for accelerating various PETs using AHE with large integer modular arithmetic. We instantiate the implementation in a Xilinx Zynq-7000 programmable SoC and provide performance evaluations in real hardware. We also investigate its efficiency in a high-end Xilinx UltraScale+ programmable SoC. We evaluate the implementation with two target use cases that have relevance in PETs: privacy-preserving computation of squared Euclidean distances over encrypted data and multi-input functional encryption (FE) for inner products. Both of them represent the first hardware acceleration results for such operations, and in particular, the latter one is among the very first published implementation results of FE on any platform.

Single-chip solution for electronics unit of a smart pressure sensor

PurposeDifferential pressure is an important technological parameter, one urgent task of which is control and measurement. To date, the lion’s share of research in this area has focused on the development and improvement of differential pressure sensors. The purpose of this paper is to develop a smart differential pressure sensor with improved operational and metrological characteristics.Design/methodology/approachThe operating principle of the developed pressure sensor is based on the capacitive measurement principle. The measuring unit of the developed pressure sensor is based on a differential capacitive sensitive element. Programmable system-on-chip (PSoC) technology has been used to develop the electronics unit.FindingsThe use of a differential capacitive sensitive element allows the unit to compensate for the influence of interference (for example, temperature) on the measurement result. With the use of PSoC technology, it is also possible to increase the noise immunity of the developed smart differential pressure sensor and provide an unparalleled combination of flexibility and integration of analog and digital functionality.Originality/valueThe use of PSoC technology in the developed smart differential pressure sensor has many indisputable advantages, as the size of the entire circuit can be minimized. As a result, the circuit has improved noise immunity. Accordingly, the procedure for debugging and changing the software of the electronics unit is simplified. These features make development and manufacturing cost effective.

Efficient FPGA Implementation of Modular Multiplication and Exponentiation

This paper presents an FPGA implementation of the most critical operations of Public Key Cryptography (PKC), namely the Modular Exponentiation (ME) and the Modular Multiplication (MM). Both operations are integrated in Hardware (HW) as Programmable System on Chip (PSoC). The processor Microblaze of Xilinx is used for flexibility. Our objective is to achieve a best trade-off between execution time, occupied area and flexibility. In order to satisfy this constraint, Montgomery Power Ladder and Montgomery Modular Multiplication (MMM) algorithms are utilized for the ME and for the MM implementations as HW accelerators, respectively. Our implementation approach is based on the digit-serial method for performing the basic arithmetic operations. Efficient parallel and pipeline strategies are developed at the digit level for the optimization of the execution time. The application for 1024-bits data length shows that the MMM run in 6.24 µs and requires 647 slices. The ME is executed in 6.75 ms, using 2881 slices.

Data acquisition and control at the edge: a hardware/software-reconfigurable approach

Today’s manufacturing facilities and processes offer the potential to collect data on an unprecedented scale. However, conventional Programmable Logic Controllers are often proprietary systems with closed-source hardware and software and not designed to also take over the seamless acquisition and processing of enormous amounts of data. Furthermore, their major focus on simple control tasks and a rigid number of static built-in I/O connectors make them not well suited for the big data challenge and an industrial environment that is changing at a high pace. This paper, advocates emerging hardware- and I/O reconfigurable Programmable System-on-Chip (PSoC) solutions based on Field-Programmable Gate Arrays to provide flexible and adaptable capabilities for both data acquisition and control right at the edge. Still, the design and implementation of applications on such heterogeneous PSoC platforms demands a comprehensive expertise in hardware/software co-design. To bridge this gap, a model-based design automation approach is presented to generate automatically optimized HW/SW configurations for a given PSoC. As a case study, a metal forming process is considered and the design automation of an industrial closed-loop control algorithm with the design objectives performance and resource costs is investigated to show the benefits of the approach.

Real time embedded system development for missile angular position acquisition through image processing

In recent days, our Indian nation moves towards “Make in India” and “Digital India” concepts. To make those concepts go live, the proposal aims at the development of an indigenous embedded system for the real time acquisition of the missile position when it is ready to be launched. The system to be developed will also communicate from the Missile Launch vehicle to the control center. It displays the position of the missile in addition to its video stream displayed on the operator’s console in control center. An extensive algorithm to calculate the angular position of the missile using the video streams captured from three different cameras will be formulated. The possibilities of real-time implementation will be explored and an extensive effort on developing a framework to implement using Field programmable Gate Arrays (FPGAs) will be carried out. The final outcome of this work will be the system on programmable chip (SoPC) implementation using FPGA for video streams, angular position display of the missile and Wireless communication between Missile launch vehicle and operator’s console in the Control center. This entire module will ensure the reliability of the angular position at which the missile has to be launched and also compactness can be achieved since the conventional computing systems will be replaced by FPGAs.