PSoC Research Articles

Accurate Low Complexity Quadrature Angular Diversity Aperture Receiver for Visible Light Positioning.

Despite the many potential applications of an accurate indoor positioning system (IPS), no universal, readily available system exists. Much of the IPS research to date has been based on the use of radio transmitters as positioning beacons. Visible light positioning (VLP) instead uses LED lights as beacons. Either cameras or photodiodes (PDs) can be used as VLP receivers, and position estimates are usually based on either the angle of arrival (AOA) or the strength of the received signal. Research on the use of AOA with photodiode receivers has so far been limited by the lack of a suitable compact receiver. The quadrature angular diversity aperture receiver (QADA) can fill this gap. In this paper, we describe a new QADA design that uses only three readily available parts: a quadrant photodiode, a 3D-printed aperture, and a programmable system on a chip (PSoC). Extensive experimental results demonstrate that this design provides accurate AOA estimates within a room-sized test chamber. The flexibility and programmability of the PSoC mean that other sensors can be supported by the same PSoC. This has the potential to allow the AOA estimates from the QADA to be combined with information from other sensors to form future powerful sensor-fusion systems requiring only one beacon.

Speed vs. efficiency: A framework for high-frequency trading algorithms on FPGA using Zynq SoC platform

Software-based technical indicators have been widely used for the stock market forecasting, aiming to predict market direction. Even though many algorithms for the software based technical indicators are presented, there are almost no hardware implementations reported in the literature. In this paper, the hardware implementation is presented for three commonly used technical indicators: Moving Average Convergence/Divergence (MACD), Relative Strength Index (RSI), and Aroon. Latency evaluation is conducted for Bitcoin and Ethereum within a single-day timeframe, utilizing the Xilinx Zynq-7000 programmable SoC XC7Z020-CLG484-1 platform.Additionally, various hardware/software (HW/SW) partitioning strategies are explored to leverage the flexibility of software alongside the performance advantages of hardware via the Zynq SoC platform. The results show that the best performing technical indicator is MACD with a speedup of 30 times over its software only counterpart. Furthermore, a hybrid design integrating multiple technical indicators is proposed, pairing MACD with RSI due to their competitive throughput values, differing by only 0.38 microseconds. This hybrid approach capitalizes on the parallel processing capabilities of hardware, enabling multiple systems to operate simultaneously.

Design of a High Speed 360-degree Panoramic Video Acquisition System Based on FPGA and USB 3.0

This paper presents a FPGA-based hardware architecture for capturing real-time panoramic images and the parallel implementation of an image stitching algorithm based on the scale-invariant feature transform (SIFT) features. First, the system transfers the images captured by five CMOS sensors to the designed FPGA board through the FMC adapter plate. Then, the system employs the FPGA-based parallel computing to extract the SIFT features and detect the best matching region and points for image registration. Finally, in order to obtain the panoramic image with smooth changes at the junctions, images of the adjacent images are fused. Using the designed FPGA platform makes it possible to extract the SIFT and stitch the images in real-time, which is not realized in most panoramic imaging systems. The panoramic system, developed using the Xilinx Zynq®-7000 all programmable SOC, can capture video of 5*640*480 images at the speed of 60 fps. To enable high-speed image transfer from the imaging system to the host computer, the USB3.0 interface with the transmission speed of 359MB/s has been developed. The real-time efficiency of the parallel system will be demonstrated by the simulations and experiments.

68-channel neural signal processing system-on-chip with integrated feature extraction, compression, and hardware accelerators for neuroprosthetics in 22 nm FDSOI.

Multi-channel electrophysiology systems for recording of neuronal activity face significant data throughput limitations, hampering real-time, data-informed experiments. These limitations impact both experimental neurobiology research and next-generation neuroprosthetics. We present a novel solution that leverages the high integration density of 22nm fully-depleted silicon-on-insulator technology to address these challenges. The proposed highly integrated programmable System-on-Chip (SoC) comprises 68-channel 0.41 μW/Ch recording frontends, spike detectors, 16-channel 0.87-4.39 μW/Ch action potentials and 8-channel 0.32 μW/Ch local field potential codecs, as well as a multiply-accumulate-assisted power-efficient processor operating at 25 MHz (5.19 μW/MHz). The system supports on-chip training processes for compression, training, and inference for neural spike sorting. The spike sorting achieves an average accuracy of 91.48 or 94.12% depending on the utilized features. The proposed programmable SoC is optimized for reduced area (9 mm2) and power. On-chip processing and compression capabilities free up the data bottlenecks in data transmission (up to 91% space saving ratio), and moreover enable a fully autonomous yet flexible processor-driven operation. Combined, these design considerations overcome data-bottlenecks by allowing on-chip feature extraction and subsequent compression.

Desarrollo de arquitectura SoPC para robot móvil basado en FPGA

In the context of the rapid progress in the field of mobile robotics, the need for efficient systems with high embedded processing power has emerged as a fundamental challenge. This paper addresses this issue by using FPGAs, devices underutilized in the literature for the development of architectures with H/S (hardware/software) co-design in mobile robots. The suitability of FPGAs for this purpose is highlighted, as they offer a balance between efficiency and low power consumption. The paper focuses on the implementation of a SoPC (System on Programmable Chip) based architecture designed specifically for an FPGA-based differential drive mobile robot. The most relevant aspects of the design are presented by means of diagrams illustrating the layout and interconnection of key components. The practical implementation of this architecture was carried out on a mobile robot whose processing unit is a DE0 Nano development board equipped with a Cyclone® IV FPGA. The results obtained reveal a successful behavior of the architecture in terms of interfacing with sensors, actuators, and data processing. The efficiency of the design is reflected in the balanced occupation of resources in the FPGA, highlighting the 67% of logical area still available for future implementations of modules for hardware acceleration. This paper demonstrates the feasibility and efficiency of FPGAs in the design of advanced architectures for mobile robots, providing a solid foundation for future research and development in the field of robotics.

A High-Performance, Low Power Research Hearing Aid featuring a High-Level Programmable Custom 22nm FDSOI SoC.

With advances in algorithmic hearing aid research, the need for high-level programmable, behind-the-ear (BTE) wearable and low-power research platforms is emerging. These can be used to test new algorithms in real-world scenarios. Although various groups are developing different portable solutions, they are not in a BTE form factor. For this reason, the devices must be worn around the neck or somewhere on the body, which causes limited mobility and can lead to inaccurate research results. Therefore, this work presents a fully integrated and functional hearing aid research platform that weighs only 5 grams and can be worn behind the ear. The platform is high-level programmable, features wireless technologies such as near-field magnetic induction (NFMI) and Bluetooth Low Energy (BLE), and integrates two micro-electro-mechanical systems (MEMS) microphones and an external speaker. The audio processor of the system is based on a new custom, low-power 22nm mixed-signal system on chip (SoC). Different real-world use cases, like a dynamic compressor, are used to evaluate the platform. With a total power consumption of 47 mW, the rechargeable device achieves a run-time of six hours. When the wireless interfaces are turned off, the power consumption drops to 31 mW, and the run-time increases to nine hours.Clinical relevance-The proposed research hearing aid demonstration platform can be used portable and outside the clinical setting for algorithmic research. With its behind-the-ear form factor and rechargeable battery, studies can be conducted for several hours without restricting patient movement in real-world scenarios.

High-Precision Dead-Time Intellectual Property Core and Its Compensation for Inverters

In the inverter circuit, there exists a specific on-off time in each power transistor. As such, to prevent a short circuit of the two switch devices on the upper and lower bridge arms, a specific dead time must be set in the pulse width modulation (PWM) and the sinusoidal pulse width modulation (SPWM) signals. In this paper, an intellectual property (IP) core that can introduce a high-precision dead time of arbitrary length into PWM or SPWM signals of the inverter is designed to increase the precision, convenience and generalization of dead time control, resulting in a boosted control accuracy of up to 10 ns. Moreover, the added Avalon bus enables IP cores to be accessed by the field programmable gate array (FPGA) processor in a standard manner and multiple IP cores of the same class can be easily incorporated. In addition, an application for setting and compensating for dead time in a three-phase inverter based on system on programmable chip (SOPC) technology is presented. With the Nios II CPU as its core, the system adopts the mean voltage compensation method to calculate the compensation voltage, and performs dead-time compensation in a feed-forward manner. The three dead-time IP cores are controlled by Avalon bus. These allow the dead time of three groups of power transistors to be accurately controlled and flexibly adjusted. The system also features the master computer communication function while boasting the advantages of flexible control, high precision and low cost.

Readjustment of a robot for educational purposes

AbstractDevelopment of control of a five degrees of freedom robot is discussed in this paper. Only two robots were made, and one of these is in the University of Miskolc. The robot was made in the 80s for educational purposes, the electronic components were obsolete and control software was missing, therefore it became necessary to perform hardware improvements, and develop a new control program. Inverse kinematics problem of the robot is solved by geometric approach to formulate the joint angles, which will form the basis of the control. A braking system containing electromagnets for the robot is constructed to balance it. A printed circuit board is designed to establish the control of the system, the central element is a Cypress PSoC 5LP platform. The development of the control program is performed in software PSoC Creator 4.4. The developed control system of the robot can receive instructions from a computer via a designed special purpose user program, which is written in Python programming language. Thanks to the improvements, the robot has become operational. Thus, the robot can serve educational purposes performing different manipulation tasks. By completing the developments, students can get to know the structure and programming of the robot, its inverse kinematics problem. This will require the development of practice-oriented tasks in the future.

On-chip hyperspectral image segmentation with fully convolutional networks for scene understanding in autonomous driving

Most of current computer vision-based advanced driver assistance systems (ADAS) perform detection and tracking of objects quite successfully under regular conditions. However, under adverse weather and changing lighting conditions, and in complex situations with many overlapping objects, these systems are not completely reliable. The spectral reflectance of the different objects in a driving scene beyond the visible spectrum can offer additional information to increase the reliability of these systems, especially under challenging driving conditions. Furthermore, this information may be significant enough to develop vision systems that allow for a better understanding and interpretation of the whole driving scene. In this work we explore the use of snapshot, video-rate hyperspectral imaging (HSI) cameras in ADAS on the assumption that the near infrared (NIR) spectral reflectance of different materials can help to better segment the objects in real driving scenarios. To do this, we have used the HSI-Drive 1.1 dataset to perform various experiments on spectral classification algorithms. However, the information retrieval of hyperspectral recordings in natural outdoor scenarios is challenging, mainly because of deficient color constancy and other inherent shortcomings of current snapshot HSI technology, which poses some limitations to the development of pure spectral classifiers. In consequence, in this work we analyze to what extent the spatial features codified by standard, tiny fully convolutional network (FCN) models can improve the performance of HSI segmentation systems for ADAS applications. In order to be realistic from an engineering viewpoint, this research is focused on the development of a feasible HSI segmentation system for ADAS, which implies considering implementation constraints and latency specifications throughout the algorithmic development process. For this reason, it is of particular importance to include the study of the raw image preprocessing stage into the data processing pipeline. Accordingly, this paper describes the development and deployment of a complete machine learning-based HSI segmentation system for ADAS, including the characterization of its performance on different embedded computing platforms, including a single board computer, an embedded GPU SoC and a programmable system on chip (PSoC) with embedded FPGA. We verify the superiority of the FPGA-PSoC over the GPU-SoC in terms of energy consumption and, particularly, processing latency, and demonstrate that it is feasible to achieve segmentation speeds within the range of ADAS industry specifications using standard development tools.

A Framework for Design, Verification, and Management of SoC Access Control Systems

System-on-chip (SoC) architectures are a heterogeneous mix of microprocessors, custom accelerators, memories, interfaces, peripherals, and other resources. These resources communicate using complex on-chip interconnect networks that attempt to quickly and efficiently arbitrate memory transactions whose behaviors can vary drastically depending on the current mode of operation and system operating state. Security- and safety-critical applications require access control policies that define how these resources interact to ensure that malicious and unsafe behaviors do not occur. <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> is a design and verification framework for on-chip access control. The core of <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> is the access control wrapper (ACW)–a high-performance yet efficient hardware module that dynamically arbitrates on-chip communications. <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> distributes ACWs across the SoC and programs them to perform local access control. <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> provides a firmware generation tool and a property-driven security verification methodology to ensure that the ACWs are properly integrated and configured. <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> security verification confirms that the ACW behaves properly at IP level. It verifies the hardware root of trust firmware configures the ACW correctly. And it evaluates system-level security threats due to interactions between shared resources. <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> is experimentally validated on a Xilinx UltraScale+ programmable SoC. Additionally, an <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> access control system is integrated into the OpenPULP multicore archtiecture that uses OpenTitan hardware root-of-trust for firmware configuration.

A low-cost shutter driver and arbitrary waveform generator for optical switching using a programmable system-on-chip (PSoC) device.

We have developed a low-cost mechanical shutter driver with integrated arbitrary waveform generation for optical switching and control using a programmable system-on-chip device. This microcontroller-based device with configurable digital and analog blocks is readily programmed using free software, allowing for easy customization for a variety of applications. Additional digital and analog outputs with arbitrary timings can be used to control a variety of devices, such as additional shutters, acousto-optical modulators, or camera trigger pulses, for complete control and imaging of laser light. Utilizing logic-level control signals, this device can be readily integrated into existing computer control and data acquisition systems for expanded hardware capabilities.

Graphene Coated Liquid Metal Droplet‐Enabled Dual‐Axis Integrated Accelerometer

AbstractThis paper presents the design, optimization, fabrication, and characterization of a novel accelerometer consisting of a graphene‐coated liquid metal proof mass integrated with laser‐induced graphene (LIG) resistive sensing elements. The sensor utilizes the unique electromechanical properties of eutectic gallium‐indium (EGaIn) liquid metal by confining an EGaIn droplet within a graphene‐patterned 3D pyramid cavity. The pyramid base structure imposes a restoring force on the droplet enabling continuous and simultaneous sensing in two directions using a single proof mass. Coating EGaIn droplet with graphene forms an interpenetrated protective shell around the droplet, enhancing its mobility and mechanical robustness. Design optimization of the sensing microelectrodes is performed to improve the sensor performance. The accelerometer performance is evaluated and characterized, demonstrating a sensitivity of ≈9.5 kΩ g−1 (978 Ω m−1 s2) and a cross‐axis sensitivity of ≈3 % with excellent repeatability (over 120 000 cycles). The sensor is fabricated using a scalable laser writing technique and integrated with a programmable system on a chip (PSoC) to function as a stand‐alone system for real‐time wireless motion monitoring and virtual game control. The developed Graphene/Liquid metal droplet‐based sensor is promising for applications of inertial sensors, inertial switches, and soft liquid metal robots with attractive electromechanical properties.

Graphene and Liquid Metal Integrated Multifunctional Wearable Platform for Monitoring Motion and Human-Machine Interfacing.

Motion sensors are an essential component of many electronic systems. However, the development of inertial motion sensors based on fatigue-free soft proof mass has not been explored extensively in the field of soft electronics. Nontoxic gallium-based liquid metals are an emerging class of material that exhibit attractive electromechanical properties, making them excellent proof mass materials for inertial sensors. Here, we propose and demonstrate a fully soft laser-induced graphene (LIG) and liquid metal-based inertial sensor integrated with temperature, humidity, and breathing sensors. The inertial sensor design confines a graphene-coated liquid metal droplet inside a fluidic channel, rolling over LIG resistive electrode. The proposed sensor architecture and material realize a highly mobile proof mass and a vibrational space for its oscillation. The inertial sensor exhibits a high sensitivity of 6.52% m-1 s2 and excellent repeatability (over 12 500 cycles). The platform is fabricated using a scalable, rapid laser writing technique and integrated with a programmable system on a chip (PSoC) to function as a stand-alone system for real-time wireless monitoring of movement patterns and the control of a robotic arm. The developed printed inertial platform is an excellent candidate for the next-generation of wearables motion tracking platforms and soft human-machine interfaces.

Gas Density Sensor Based on PSoC5

A significant part of all types of measurements performed in modern industry and science are measurements of gas, liquid or other media. This is important because there are many processes where you need to clearly control the parameters of the environment - pressure, density, etc. The object of research are MEMS gas density sensors. The subject of the research is to eliminate the shortcomings of existing similar systems, increase the accuracy of measurement and range of measured gas pressures and safe operation of the system in critical conditions. The aim of the work is to implement a gas density sensor based on a crystal, using auxiliary functional modules, to monitor the operation of the system and to obtain a sophisticated functional device that will be easy to use. Several prototypes are considered, where a miniature cantilever is used as a sensitive element. The disadvantage of such systems is that the accuracy of measurement depends on the support of the cantilever and the gas pressure. Also in the prototype [3] it is noted that the measurement time of one sample lasts about 2 minutes, which is very significant. In the course of work the methods of determination of thermophysical parameters of the environment with use of primary converters on MEMS technology which are made on structure of a heater, a sensitive element and passive components are analyzed. Calculations for determination of gas density are also described. The implementation of a complete, functional sensor for measuring gas parameters based on a programmable system on a crystal based on Cypress PSoC 5 is considered. This system allows us to implement a complex measuring device on almost one crystal because this system has in its structure a certain set of already built-in analog and digital units. The main advantage of PSoC5 is the ability to dynamically reconfigure the system during operation. That is, having one set of elements, we can build on it a number of different schemes without stopping the measurement process. PSoC Designer software configures built-in units such as DAC, iDAC, ADC. The configuration of these units and connection to them of external elements, such as thermistors and a thermal heater are given. Simulation of the given scheme is carried out and results in a graphic kind are resulted. The main principle of the device is the dependence of temperature attenuation on the environment. The idea is to compare the phase shift between two harmonic signals. One signal is a reference signal, and the other is a signal that is recorded by a thermal sensor after the temperature wave passes through the measuring medium. Since this signal will pass with a certain delay then the phases of the reference signal and the measured will be shifted. Therefore, the phase difference between these signals will depend on the density of the medium through which the heat wave passes. In the conclusion of work both advantages and lacks of the offered method which have been proved on the basis of comparison with other already known similar methods are considered.

A Formal Verification Method for the SOPC Software

System on programmable chip (SOPC) is a kind of system on a programmable chip. The system architecture is superior to the traditional design pattern. The system has an <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -chip bus between the processor and the programmable logic, which forms a high bandwidth, low latency, connection, and has rich flexible customization of IP. It also has advantages of low power consumption and high performance. The application in the field of high reliable proportion rising year by year. However, the change of system architecture and the expansion of software scale have brought great impact on the simulation test method and the physical test method. The existing dynamic testing methods are based on limited testing scenarios to investigate the system. It is difficult to find hidden errors in the design of complex connection segments, such as the errors in the <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -chip bus transmission, the errors in the hardware and software coupling, and so on. Due to system scale of the state-space explosion problem and various forms IP, SOPC cannot apply formal verification techniques. In this article, we propose a SOPC formalized validation framework. It is based on polymorphous IP abstraction modeling, common formal properties analysis, and modeling methods in system architecture and other high-risk areas. The experimental results show that the proposed algorithm and the established SOPC formal verification framework can introduce the formal verification technique to SOPC high-risk area verification, and it can be used as the guidance of SOPC formal verification.

Smart Irrigation System Deploying PSoC and Wireless Sensor Network

Traditional agricultural systems require huge amount of power for field watering. This paper deals with designing of a smart irrigation system, that helps farmers water their agricultural fields using innovative technology. There is no need to frequently apply water across entire fields. Instead, they can use the minimum quantities required and target very specific areas. To increase the productivity, the newer technology is more helpful. The important factors of agricultural sectors are temperature, water and fertilizer management. On survey it is found that water management is an important issue, hence the research work is focused on the water and moisture management of soil. In last decades advancements in technology is tremendous. Programmable System-on-chip (PSoC) integrate configurable analog and digital blocks which makes it different from traditional microcontrollers and is a miniaturized device. It combines the architectures of FPGA and ASIC. Deploying the advanced features of PSoC it is proposed to design and develop the smart irrigation system based on PSoC and Wireless Communication Technology. To achieve the desired goal, the data from the soil moisture sensor is processed and the data is calibrated in real units. After that it is displayed on LCD and using wireless technology same is transmitted towards the base station. The smart NRF24L01 transceiver operates on IEEE 802.15.4 Industrial Scientific and Medical (ISM) Band. Moreover, the base station of Wireless Sensor Network is designed to demonstrate collected information in user friendly format.

A modular and flexible data acquisition system for a cosmic rays detector network

In this paper, we describe a modular data acquisition system developed as the foundation of a cosmic ray detector network. Each detector setup (henceforth referred as a station) is composed of an independent hardware device that can be controlled and read-out through the Internet. This device is designed to acquire and process the signal of up to eight different detector planes. Each of these detector planes uses plastic scintillator slabs that are optically coupled to silicon photomultipliers (SiPM). Within a single station, different geometries and plane orientations are possible using the same baseline design. The main readout is based on a programmable system-on-a-chip (PSoC), a flexible and re-configurable commodity hardware that is used to implement the trigger and timing logic. A Time to Digital Converter (TDC) is used to determine the precise timing of the event relative to a GPS timing signal and to estimate the signal amplitude through the Time-over-Threshold (ToT) method. An auxiliary set of sensors provide environmental information and station detector planes orientation that, together with other operation data, are periodically sent to a server using the MQTT protocol. Data is cached using an in-memory database for online monitoring and further persisted into a SQL database for offline analysis. The server framework is based in software application containers allowing easy replication of the server infrastructure.

Humidity monitoring of neonatal intensive care unit based on programmable system on chip

A premature baby's treatment takes place in the Neonatal Intensive Care Unit (NICU). The NICU is an isolated room and it consists of a number of baby incubators and measuring, monitoring devices such as incubator, overhead heater, monitors, ambient oxygen analyser, intravenous drip, feeding pump and tubes, power supply, ventilator monitor, ventilator, etc. The measuring and controlling parameters are temperature of baby and baby incubator, oxygen level, CO2 level, pulse rates, humidity, light intensity etc. This research paper deals with monitoring the humidity of baby incubators. The increase or decrease of humidity levels causes an effect on the baby's health. High humidity creates problems such as heat exhaustion, heat stroke and an overproduction of mold causes allergies. The monitoring and controlling of humidity are the most important parameters in NICU. The humidity of the baby incubator is monitored using a humidity sensor. The sensing data is given to the Programmable System on Chip (PSoC). The system under investigation is designed successfully and reported in this paper.

Intelligent adjustable-speed drive on an FPGA

This paper addresses the design, simulation and implementation of a PI-like fuzzy controller to adjust the velocity of an armature-controlled DC motor using hardware/software co-design. Fuzzy control and digital pulse width modulation (PWM) techniques are used as computational solution, while the implementation is carried on a reconfigurable hardware platform. This controller is designed with four considerations in mind: design integration, robustness, reduced complexity and flexibility. Computationally intensive tasks are implemented as hardware accelerators using VHDL, data flow and control are implemented in software using system-on-programmable-chip (SoPC) approach. With this paradigm, we get the robustness of fuzzy control, the best of software programmability of Nios®-II and the hardware reconfigurability of the FPGA. The model was synthesised using Quartus®II and targeted at a Cyclone-II FPGA. Computer simulation results show the effectiveness and merit of this process. The real-time applicability of this controller is exemplified on a motor provided with a tachogenerator mounted on its shaft.

Testing a Fault Tolerant Mixed-Signal Design Under TID and Heavy Ions

This work presents results of three distinct radiation tests performed upon a fault-tolerant data acquisition system comprising a design diversity redundancy technique. The first and second experiments are Total Ionizing Dose (TID) essays, comprising gamma and X-ray irradiations. The last experiment considers single event effects, in which two heavy ion irradiation campaigns are carried out. The case study system comprises three analog-to-digital converters and two software-based voters, besides additional software and hardware resources used for controlling, monitoring and memory management. The applied Diversity Triple Modular Redundancy (DTMR) technique, comprises different levels of diversity (temporal and architectural). The circuit was designed in a programmable System-on-Chip (PSoC), fabricated in a 130nm CMOS technology process. Results show that the technique may increase the lifetime of the system under TID if comparing with a non-redundant implementation. Considering the heavy ions experiments the system was proved effective to tolerate 100% of the observed errors originated in the converters, while errors in the processing unit present a higher criticality. Critical errors occurring in one of the voters were also observed. A second heavy-ion campaign was then carried out to investigate the voters reliability, comparing the dynamic cross-section of three different software-based voter schemes implemented in the considered PSoC.