System-on-chip Implementation Research Articles

Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and Trends.

This paper reviews the evolution of methodologies and tools for modeling, simulation, and design of digital electronic system-on-chip (SoC) implementations, with a focus on industrial electronics applications. Key technological, economic, and geopolitical trends are presented at the outset, before reviewing SoC design methodologies and tools. The fundamentals of SoC design flows are laid out. The paper then exposes the crucial role of the intellectual property (IP) industry in the relentless improvements in performance, power, area, and cost (PPAC) attributes of SoCs. High abstraction levels in design capture and increasingly automated design tools (e.g., for verification and validation, synthesis, place, and route) continue to push the boundaries. Aerospace and automotive domains are included as brief case studies. This paper also presents current and future trends in SoC design and implementation including the rising, evolution, and usage of machine learning (ML) and artificial intelligence (AI) algorithms, techniques, and tools, which promise even greater PPAC optimizations.

Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip

Recent research has shown interest in adopting the RISC-V processors for high-reliability electronics, such as aerospace applications. The openness of this architecture enables the implementation and customization of the processor features to increase their reliability. Studies on hardened RISC-V processors facing harsh radiation environments apply fault tolerance techniques in the processor core and peripherals, exploiting system redundancies. In prior work, we present a hardened RISC-V System-on-Chip (SoC), which could detect and correct radiation-induced faults with limited fault awareness. Therefore, in this work, we propose solutions to extend the fault observability of the SoC implementation by providing error detection and monitoring. For this purpose, we introduce observation features in the redundant structures of the system, enabling the report of valuable information that supports enhanced radiation testing and support the application to perform actions to recover from critical failures. Thus, the main contribution of this work is a solution to improve fault awareness and the analysis of the fault models in the system. In order to validate this solution, we performed complementary experiments in two irradiation facilities, comprehending atmospheric neutrons and a mixed-field environment, in which the system proved to be valuable for analyzing the radiation effects on the processor core and its peripherals. In these experiments, we were able to obtain a range of error reports that allowed us to gain a deeper understanding of the faults mechanisms, as well as improve the characterization of the SoC.

Embedded Machine Learning Using a Multi-Thread Algorithm on a Raspberry Pi Platform to Improve Prosthetic Hand Performance.

High accuracy and a real-time system are priorities in the development of a prosthetic hand. This study aimed to develop and evaluate a real-time embedded time-domain feature extraction and machine learning on a system on chip (SoC) Raspberry platform using a multi-thread algorithm to operate a prosthetic hand device. The contribution of this study is that the implementation of the multi-thread in the pattern recognition improves the accuracy and decreases the computation time in the SoC. In this study, ten healthy volunteers were involved. The EMG signal was collected by using two dry electrodes placed on the wrist flexor and wrist extensor muscles. To reduce the complexity, four time-domain features were applied to extract the EMG signal. Furthermore, these features were used as the input of the machine learning. The machine learning evaluated in this study were k-nearest neighbor (k-NN), Naive Bayes (NB), decision tree (DT), and support vector machine (SVM). In the SoC implementation, the data acquisition, feature extraction, machine learning, and motor control process were implemented using a multi-thread algorithm. After the evaluation, the result showed that the pairing of the MAV feature and machine learning DT resulted in higher accuracy among other combinations (98.41%) with a computation time of ~1 ms. The implementation of the multi-thread algorithm in the pattern recognition system resulted in significant impact on the time processing.

An enhanced flower pollination algorithm‐based chaff point generation method with hardware implementation in WBAN

SummaryIn wireless body area networks (WBAN), device authentication and key agreement are the critical issues. In any real‐world cryptographic system, issues like these can be handled by one of the most practical bio‐cryptosystem schemes popularly known as fuzzy vault (FV). The secret key is encoded in a polynomial equation merged with physiological value and then combined with chaff (noise) points forming the FV. The most critical and computational intensive task in the FV is the chaff point generation, that is used to hide the valid point inside the vault pattern. In this paper, we propose an Enhanced Flower Pollination Algorithm based Chaff Point generation method with Hardware (EFPCH) implementation and have been proved to be a computationally fast and feasible algorithm for hardware implementation. The security of the FV depends on the infeasibility of the polynomial reconstruction and also in large number of chaff point. The existing methods for chaff point generation had taken less number of valid points and generate a maximum of 200 chaff points. But in our experimental result, we generated large number of chaff point (1:12) with a considerable amount of valid points over the existing algorithm. This work describes the key agreement model and implementation step required for identifying External programmer attached to the patient pacemaker. However, existing key agreement schemes have too many computational intensive tasks, making it unsuitable for system‐on‐chip (SoC) implementation. In the result of the described work, a practical SoC implementation of the wireless environment in WBAN is experimented. The results show that our proposed model has a more efficient implementation in generating larger chaff points and performs better than other current methods.

FPGA Prototyping of Micro-Blaze soft-processor based Multi-core System on Chip

The increased demand for processor-level parallelism has many-folded the challenges for SoC designers to design, simulate and verify/validate today’s Multi-core System-On-Chip (SoC) due to the increased system complexity. There is also a need to reduce the design cycle time to produce a complex multi-core SOC system thereby the product can be brought into the market within an affordable time. The Computer-Aided Design (CAD) tools and Field Programmable Gate Arrays (FPGAs) provide a solution for rapidly prototyping and validating the system. This paper presents an implementation of multi-core SoC consisting of 6 Xilinx Micro-Blaze soft-core processors integrated to the Zynq Processing System (PS) using IP Integrator and these cores will be communicated through AXI bus. The functionality of the system is verified using Micro-Blaze system debugger. The hardware framework for the implemented system is implemented and verified on FPGA.

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays * * Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication.

Design of a multi-frequency Bio-Impedance Spectroscopy system Analog Front-End and Digital Back-End with system on-chip implementation

In this paper, the design of an on-board and system on-chip Bio-Impedance Spectroscopy (BIS) mixed-signal system is presented. It consists of a Direct Digital Synthesis Sine-Wave Generator (DDS-SWG), an Analog Front-End (AFE), an Analog-Digital Converter (ADC), and a Digital Back-End implemented on a Field Programmable Gate Array (FPGA). The FPGA drives the ADC, the DDS-SWG, and the LCD. The AFE consists of a high output impedance Load-In-Loop Current Source (LL-CS) and High Common-Mode Rejection Ratio (CMRR) Instrumentation Amplifiers (IA). It uses a simple and straightforward impedance extraction algorithm using division and constant multiplication. Furthermore, a method that extends the AFE implementation to BIS tomography applications is presented offering low power dissipation and more chip area budget. The CMOS implementation of the AFE and the digital ASIC using TSMC 0.18µm 1P6M are also presented. The CMOS AFE has been optimized to dissipate low power even when operating at high frequency. The system forms part of a platform that aims to predict a urolithiasis (urinary stone) event where qualitative measures of K+, Ca2+, Cl− and Na+ concentrations in urine can be obtained through impedance/ conductivity.

Optimized Design of SoC-based Control System for Multi-axis Drive

This study presents an optimized system-on-chip (SoC) based multi-axis control system for permanent magnet synchronous motor (PMSM). The multi-axis control system becomes considerably complex with increasing controlled axes and complicated control algorithms. This paper aims to provide a balanced design considering control performance, hardware constrains and feasibility. To cope with this problem, the system design is optimized by using pipeline and time division multiplexing technology. Due to the optimized architecture and the computation capability of SoC, the performance of the whole system can be preserved. To demonstrate this, a SoC implementation of the control system is presented and comprehensively analyzed. Herein, the vector control in the current loop is explained and an anti-windup proportional-integral (PI) controller is adopted in the speed loop. The sampling frequencies of the current loop and the speed loop are 16 KHz and 4 KHz respectively. Consequently, the execution time is several microseconds with reasonable consumed resources. Experimental results are shown to prove the efficiency of the proposed SoC-based solution. DOI: http://dx.doi.org/10.5755/j01.eee.20.7.4848

FPGA‐based embedded platform for fiber optic gyroscope signal denoising

SUMMARYThis paper presents System on Chip (SoC) implementation of a proposed denoising algorithm for fiber optic gyroscope (FOG) signal. The SoC is developed using an Auxillary Processing Unit of the proposed algorithm and implemented in the Xilinx Virtex‐5‐FXT‐1136 field programmable gate array. SoC implementation of this application is first of its kind. The proposed algorithm namely adaptive moving average‐based dual‐mode Kalman filter (AMADMKF) is a hybrid of adaptive moving average and Kalman filter (KF) technique. The performance of the proposed AMADMKF algorithm is compared with the discrete wavelet transform and KF of different gains. Allan variance analysis, standard deviation and signal to noise ratio (SNR) are used to measure the efficiency of the algorithm. The experimental result shows that AMADMKF algorithm reduces the standard deviation or drift of the signal by an order of 100 and improves the SNR approximately by 80 dB. The Allan variance analysis result shows that this algorithm also reduces different types of random errors of the signal significantly. The proposed algorithm is found to be the best suited algorithm for denoising the FOG signal in both the static and dynamic environments. Copyright © 2013 John Wiley & Sons, Ltd.

Biometric encryption based on a fuzzy vault scheme with a fast chaff generation algorithm

Fuzzy vault is a scheme that complements traditional cryptographic security systems by combining it with biometric authentication to overcome the security vulnerability inherent in cryptographic key storage. Biometric encryption systems based on fuzzy vault scheme are suitable for stand-alone security and authentication devices in the form of system-on-chip (SoC). However, the current fuzzy vault scheme has too many compute-intensive processes to make this feasible for SoC implementation. The most critical but compute-intensive function in the fuzzy vault scheme is the chaff generation which produces noise (chaff) points that hide the valid points inside the vault template. In this paper, we propose a new chaff generation algorithm which is computationally fast and viable for hardware acceleration by employing simple arithmetic operations. Complexity study shows that our algorithm has a complexity of O(n2), which is a significant improvement over the existing method that exhibits O(n3) complexity. Our experimental results show that, to generate 500 chaff points, the proposed algorithm gives a performance speed-up of over 140 times over existing Clancy’s algorithm. With the new chaff generation algorithm, it becomes much more amenable to implement the fuzzy vault scheme in the resource-constrained environment of system-on-chip.

SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications

With increasing design complexity, the gap from ESL (Electronic System Level) design to RTL synthesis becomes more and more crucial to many industrial projects. Although several behavioral synthesis tools exist to automatically generate synthesizable RTL code from C/C++/SystemC-based input descriptions and software generation for embedded processors is automated as well, an efficient ESL synthesis methodology combining both is still missing. This article presents SystemCoDesigner, a novel SystemC-based ESL tool to automatically optimize a hardware/software SoC (System on Chip) implementation with respect to several objectives. Starting from a SystemC behavioral model, SystemCoDesigner automatically extracts the mathematical model, performs a behavioral synthesis step, and explores the multiobjective design space using state-of-the-art multiobjective optimization algorithms. During design space exploration, a single design point is evaluated by simulating highly accurate performance models, which are automatically generated from the SystemC behavioral model and the behavioral synthesis results. Moreover, SystemCoDesigner permits the automatic generation of bit streams for FPGA targets from any previously optimized SoC implementation. Thus SystemCoDesigner is the first fully automated ESL synthesis tool providing a correct-by-construction generation of hardware/software SoC implementations. As a case study, a model of a Motion-JPEG decoder was automatically optimized and implemented using SystemCoDesigner. Several synthesized SoC variants based on this model show different tradeoffs between required hardware costs and achieved system throughput, ranging from software-only solutions to pure hardware implementations that reach real-time performance for QCIF streams on a 50MHz FPGA.

Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A multicore system-on-chip (SoC) has been developed for various applications (recognition, inference, measurement, control, and security) that require high-performance processing and low power consumption. This SoC integrates three types of synthesizable processors: eight CPUs (M32R), two multi-bank matrix processors (MBMX), and a controller (M32C). These processors operate at 1 GHz, 500 MHz, and 500 MHz, respectively. These three types of processors are interconnected on this chip with a high-bandwidth multi-layer system bus. The eight CPUs are connected to a common pipelined bus using a cache coherence mechanism. Additionally, a 512-kB L2 cache memory is shared by the eight CPUs to reduce internal bus traffic. A multi-bank matrix processor with 2-read/1-write calculation and background I/O operation has been adopted. The 1-GHz CPU is realized using a delay management network which consists of delay monitors that can be applied for any kind of application or process technology. Our configurable heterogeneous architecture with nine CPUs and two matrix processors reduces power consumption by 45%. </para>

Developing e-commerce business models for enabling silicon intellectual property transactions

Integrated Circuit (IC) design productivity has failed to keep pace with Moore's Law in the past decade; thus, a 'design productivity gap' between the increase in IC design complexity and increased productivity has emerged. As the IC industry migrates to the System-On-Chip (SOC) era, the nature of Silicon Intellectual Property (SIP), which can narrow the 'design productivity gap', has made SIP critical for the design and implementation of a complex SOC. There are two major categories of SIP problems, technical and business; both are based on current SIP transaction business processes. The primary purpose of this paper is to develop e-commerce business models to resolve complex technical and business issues in SIP transactions and thus enable the business more fully online. The benefits of the proposed e-commerce business models and efficiency improvements to SOC designs regarding the leveraging of the proposed models are discussed.

Microelectromechanical systems and system-on-chip connectivity

The interconnection of microelectromechanical systems (MEMS) and other devices to a system-on-chip (SoC) implementation is described. MEMS technology can be used to fabricate both application specific devices and the associated micropackaging system that will allow for the integration of devices or circuits, made with non-compatible technologies, with a SoC environment. In the primary example presented, MEMS technology has been used to develop an acoustical array sensor for a hearing instrument application and also to provide a custom micropackaging solution suitable for in-the-ear canal implantation. A MEMS based modular micropackaging solution consisting of MEMS socket submodules and an insertable/removable microbus card has been developed to provide the necessary packaging and connectivity requirements. The modular socket concept can also be used for many other purposes, such as temporarily connecting a CMOS die to a SoC implementation of a die tester using MEMS based cantilevered bridge-type microspring contacts to provide connectivity to the die under test.