System LSI Research Articles

219 SDSI-Cubic手法によるシステムLSIのシステムデザインに関する研究

219 SDSI-Cubic手法によるシステムLSIのシステムデザインに関する研究

TeV gamma-rays from accreting magnetars in massive binaries

We consider the neutron star (NS) of the magnetar type inside the massive binary system. We determine the conditions under which the matter from the stellar wind can penetrate the inner magnetosphere of the magnetar. At some distance from the NS surface, the magnetic pressure can balance the gravitational pressure of the accreting matter creating very turbulent, magnetized transition region. It is suggested that this region provides good conditions for acceleration of electrons to relativistic energies. These electrons lose energy on the synchrotron process and the Inverse Compton (IC) scattering of the radiation from the nearby massive stellar companion, producing high energy radiation from the X-rays up to $\sim$TeV $\gamma$-rays. The primary $\gamma$-rays can be farther absorbed in the stellar radiation developing the IC $e^\pm$ pair cascade. We calculate the synchrotron X-ray emission from primary electrons and secondary $e^\pm$ pairs and the IC $\gamma$-ray emission from the cascade process. It is shown that the quasi-simultaneous observations of the TeV $\gamma$-ray binary system LSI +61 303 in the X-ray and the TeV $\gamma$-ray energy ranges can be explained in such an accreting magnetar model.

Cadence and NEC electronics announce encounter digital implementation system to support NEC Electronics' system LSI with built-in V850 CPU core

Cadence and NEC electronics announce encounter digital implementation system to support NEC Electronics' system LSI with built-in V850 CPU core

Impact of Mechanical Stress on Hot-Carrier Lifetime and Time-Dependent Dielectric Breakdown in Downscaled Complimentary Metal–Oxide–Semiconductor

The interactions of hot-carrier (HC) instability and time-dependent dielectric breakdown (TDDB) with mechanical stress are investigated intensively. We determined from experimental data that the hot-carrier injection in p-type metal–oxide–semiconductor field-effect transistors (PMOSFETs) occurs at the center of the channel under the most severe stress condition of Vgs = Vds and that a physical mechanism similar to negative bias temperature instability (NBTI) is responsible for degradation at room temperature, as confirmed from the result of hydrodynamic simulations. We demonstrated that mechanical stress resulting from the sidewall spacer accelerates this hot carrier degradation in short-channel PMOSFETs. This phenomenon is not observed in the n-type MOSFET (NMOSFET) case. We also observed that the anomalous degradation in TDDB for downsized NMOSFETs is caused by the compressive stress from shallow trench isolation (STI) and shows strong correlation with hydrogen processes. The optimization of hydrogen processes and mechanical stress is indispensable for a highly reliable system LSI in the future.

An Integrated Platform for Digital Consumer Electronics

This paper describes the architecture of an integrated platform developed for improving the development efficiency of system LSIs built into digital consumer electronics equipment such as flat-panel TVs and optical disc recorders. The reason for developing an integrated platform is to improve the development efficiency of system LSIs that serve the principal functions of the said equipment. The key is to build a common interface between each software layer, with the system LSI located at the lowest layer. To make this possible, the hardware architecture of the system LSI is divided into five blocks according to its main functionality. In addition, a middleware layer is placed over the operating system to improve the ease of porting old applications and developing new applications in the higher layer. Based on this platform, a system LSI called UniPhier™ has been developed and used in 156 product families of digital consumer electronics equipment (as of December 2008).

2123 次世代半導体デバイスにおけるシステムデザイン手法構築の基礎的検討(OS6-1 モデル駆動型の製品システム開発,OS6 モデル駆動型の製品システム開発)

Semiconductors that brings about advanced information society, was made its performance to improve by miniaturization. However semiconductors, as a product system, is reaching near-term economic and physical limitations. And 3D integration, such as 3D-SiP, is expected as the break through. But traditional design method based on only scaling rule can't apply to this. Therefore it is difficult to decide the development direction of the next generation semiconductor device in early phase of system LSI design. In addition, design method based on design rule has various problems. So we need to construct design method for system LSI. As a solution for these problems, we build up a parametric model and a workflow for proper system LSI structure including 3D-SiP. As a result, we get the proper structure of next generation semiconductor device by using the parametric model and workflow.

An interface and communication technique between circuit blocks in system LSI

AbstractIn large‐scale System LSI/SoC, how to standardize the communication method between diversified cores becomes one of the important problems, and various study reports have been done.We propose a new method to solve the problem, where the communication between cores is limited only to using message+parameters format. As the communication mechanism between IP cores and a common bus, we introduced the architecture, ACU, common to every core with various I/O functions, and it can be realized with a scale of less than 5 K gates.As the paradigm of Globally‐Asynchronous Locally‐Synchronous (GALS) system is attracting attention, this method is believed to be a good suggestion as a communication mechanism between local IP cores. © 2009 Wiley Periodicals, Inc. Electron Comm Jpn, 91(12): 9–15, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecj.10008

From Vertical to Horizontal Inter-Firm Cooperation: Dynamic Innovation in Japan's Semiconductor Industry

In the 1990s, Japanese semiconductor manufacturers lost international competitiveness, failing to maintain their technological leadership. Their innovative dynamics in the old techno-governance structure based on vertical intra- and inter-firm cooperation faced limitations; they became entrapped in a DRAM-based technological trajectory. Faced by disrupting contingencies, how did they change relations with firm- and technology-related actors in ways sufficient to develop a new techno-governance structure? Through their micro-level strategies they shifted from vertical intra- and inter-firm relations to horizontal ones, while through their macro-level strategies they developed coordinating mechanisms with technology-related actors in order to consolidate innovative capability for developing the system LSI. These strategies resulted in a complex mix of modularized-product-based competition and cooperation in addition to reviving collective projects, some running even without government subsidy. Such developments, though characterized as new, remain an extension of the Japanese institutional inheritance; namely, an emphasis on a strategic mix of cooperation and competition, but with a revised understanding of cooperation. Thus, this paper analyzes how institutions restrict innovative dynamics through techno-governance structure, while they also transform path-dependently as actors struggle to develop a new structure to cope with threatening contingencies.

Status and results of the MAGIC telescope

The MAGIC telescope is an imaging air Cherenkov telescope for very high energy gamma-ray astronomy. The scientific outcome of MAGIC at the end of its second cycle of observations includes outstanding results in both galactic and extragalactic physics. Among them the observation of periodic gamma-ray emission from the galactic binary system LSI+61, an unprecedented fast variability in the flux of the active galaxy Mrk 501 and the discovery of several new gamma-ray sources. The status and ongoing upgrades of the experiment, and a review of the main physics results are presented.

Basic Consecutive System Consisted of Design, Process and Estimation of a Fundamental Integrated Circuit Education System

The progress of integrated-circuits technology in recent years has enabled a large performance-increase of system LSI. As it is needed long time to study the knowledge of the system LSI such as design, semiconductor process, and estimation of device, it is hard to study system LSI technology for company man and students. The basic consecutive system consisted of design, process and estimation of a fundamental IC system was studied.

An Interface and Communication Technique between Circuit Blocks in System LSI

In large-scale System-LSI/SoC, how to standardize the communication method between diversified cores becomes one of the important problems, and various study reports have been done.We propose a new method to solve the problem, where the communication between the cores is limited only to using message + parameters format. As the communication mechanism between IP cores and a common bus, we introduced the architecture, ACU, common to every core with various I/O functions, and it can be realized with less than 5k gates scale.As the paradigm of Globally-Asynchronous Locally-Synchronous(GALS) system is attracting attention, this method is believed to be a good suggestion as a communication mechanism between local IP cores.

A Single Chip H.264/AVC HDTV Encoder/Decoder/Transcoder System LSI

A new single chip HDTV H.264 codec system LSI was designed using flexible codec architecture. It supports HP@L4.1 with full 1920x1080 resolution. The LSI supports MPEG2 and JPEG as well. The chip integrates one encoder and two decoders, which work independently and can be used in flexible ways including transcoding. It also integrates almost all the necessary functions for digital consumer application including an audio codec, graphics and video circuitry, peripherals, and a generic microprocessor.

Inverse Compton e pair cascade model for the -ray production in massive binary LSI +61 303

We apply an inverse Compton e ± pair cascade model for γ-ray production in the massive binary system LSI +61° 303 assuming that electrons are accelerated already inside the inner part of the jet launched by the compact object. γ-ray spectra, affected by the cascade process, and lower energy spectra, from the synchrotron cooling of the highest energy electrons in the jet, are calculated as a function of the phase of this binary system. γ-ray spectra expected in such a model have different shape than those ones produced by electrons in the jet directly to observer. Moreover, the model predicts clear anticorrelation between γ-ray fluxes in the GeV (1-10 GeV) and TeV (>200 GeV) energy ranges with the peak of the TeV emission at the phase ∼0.5 (the peak half-width ranges between the phases ∼0.4-0.9, for the inclination of the binary system equal to 60°, and ∼0.4-0.1 for 30°). The fine features of TeV γ-ray emission (fluxes and spectral shapes) as a function of the phase of the binary system are consistent with recent observations reported by the MAGIC collaboration. Future simultaneous observations in the GeV energies (by the GLAST and AGILE telescopes) and in the TeV energies (by the MAGIC and VERITAS telescopes) should test other predictions of the considered model supporting or disproving the hypothesis of acceleration of electrons already in the inner part of the microquasar jets.

System LSI: Challenges and Opportunities

Scaling of CMOS Integrated Circuit is becoming difficult, due mainly to rapid increase in power dissipation. How will the semiconductor technology and industry develop? This paper discusses challenges and opportunities in system LSI from three levels of perspectives: transistor level (physics), IC level (electronics), and business level (economics).

Digital Television Receiver for ISDB

This paper presents the digital high-definition television (HDTV) receiver for the ISDB system. It receives 8 phase shift keying (8-PSK) satellite broadcast and orthogonal frequency division multiplex (OFDM) terrestrial broadcast. It decodes the MPEG2 audio/video stream and converts the original HDTV picture to the various display formats. It also decodes the interactive data broadcast content written in the Broadcast Markup Language (BML) and display the graphical picture on the TV screen. The Conditional Access System (CAS) is used not only for the pay TV but also for copy protection of the broadcast contents. The receiver has an Ethernet terminal that enables Internet connection for various applications. The receiver system design, software architecture, and LSI configuration are described in this paper.

シリコンシーベルト福岡のシステムＬＳＩ設計人材育成―社会人教育―

The Silicon Sea Belt Fukuoka Project was pushed forward in Fukuoka Prefecture in 2001 and has promoted human resource development of System LSI design engineers. Under liaising of industry, academia and government, “College of System LSI, Fukuoka” was founded and QUBE (Q-shu University hardware/software Borderless system design Education program) has been started aiming to establish education system for working engineers. In this paper, results of our challenge and future prospects are described.

Wire Length Distribution Model for System LSI

This paper concerns a new model for estimating the wire length distribution (WLD) of a system-on-a-chip (SoC). The WLD represents the correlation between wire length and the number of interconnects, and we can predict circuit performances such as power consumption, maximum clock frequency, and chip size from the WLD. A WLD model considering core utilization has been proposed, and the core utilization has a large impact on circuit performance. However, the WLD model can treat only a one-function circuit. We propose a new WLD model considering core utilization to estimate the wire length distribution of SoC, which consists of several different-function macroblocks. We present an optimization method to determine each core utilization of macroblocks.

Responsive Multithreaded Processor for Distributed Real-Time Systems

The Responsive MultiThreaded (RMT) Processor is a system LSI that integrates almost all functions for parallel/distributed real-time systems including robots, intelligent rooms/buildings, ubiquitous computing systems, and amusement systems. Concretely, the RMT Processor integrates real-time processing (RMT Processing Unit), real-time communication (Responsive Link II), computer I/O peripherals (DDR SDRAM I/Fs, DMAC, PCI-X, USB2.0, IEEE1394, etc.), and control I/O peripherals (PWM generators, pulse counters, etc.). The RMT Processor, with a design rule of 0.13<I>μ</I>m CMOS Cu 1P8M and a die size 10.0mm square, was fabricated by TSMC. The RMT Processing Unit (RMT PU) executes eight prioritized threads simultaneously using fine-grained multithreading based on priority, called the RMT architecture. Priority of real-time systems is introduced into all functional units, including cache, fetch, and execution, so the RMT PU guarantees real-time execution of prioritized threads. If resource conflicts occur at functional units, higher priority threads overtake lower priority threads. Flexible powerful vector operation units for multimedia processing are also designed. System designers use on-chip functions easily by connecting required I/Os to this chip and the designers realize distributed control by connecting several RMT Processors with their own functions via Responsive Link II.

Embedded Ferroelectric Memory Technology With Completely Encapsulated Hydrogen Barrier Structure

A 0.18-/spl mu/m system LSI embedded ferroelectric memory (FeRAM) operating at a very low voltage has been developed for the first time. The low-voltage operation has been attained by newly developed stacked ferroelectric capacitors completely encapsulated by hydrogen barriers, which enable us to eliminate hydrogen reduction of the ferroelectric thin film during the back end of the line process including FSG, tungsten CVD (W-CVD), and plasma CVD SiN (p-SiN) passivation. A fabricated 1-Mbit one-transistor one-capacitor SrBi/sub 2/(Ta/sub x/Nb/sub 1-x/)/sub 2/O/sub 9/ (SBTN)-based embedded FeRAM operates at a low voltage of 1.1 V and ensures the endurance cycles up to 10/sup 12/ at 85/spl deg/C and the data retention time up to 1000 h at 125/spl deg/C, which is the most promising for mass production of 0.18-/spl mu/m low-power system LSI-embedded FeRAM and beyond.

Customer value creation through customer-as-innovator approach: a case study of video processing LSI development

Changes in the business process brought about by the Customer-as-Innovator approach in some fields of product and service development have been making progress in recent years. This approach has the potential to realise dramatic improvements in development cost cuts, development times, and production volume for customers, developers, and producers. It may also enable significant reforms in existing value chains. This paper describes a case study involving the development of a multimedia video processing system LSI, positioned as a key semiconductor device in information networks of the future. This paper examines and analyses how advances in system LSI toolkits and other areas have been bringing about a shift in the system LSI development process from developers and producers (order recipients) to customers (order issuers).