System-level Timing Research Articles

Causal Path Identification for Timed and Sequential Circuits

Self-timed and pulse mode circuit modules are often implemented using combinational logic with feedback, or require timing constraints for the circuit to function correctly. Identifying causal paths through these circuit modules is a fundamental requirement to enable automatic system level timing closure, performance analysis, and timing-driven optimizations when using static timing analysis algorithms. A methodology and algorithm for identifying causal paths in cyclic sequential circuits under arbitrary timing models are presented. The algorithm identifies causal paths in a sequential circuit implemented with standard cell gates. The algorithm is demonstrated by identifying causal paths for over 100 asynchronous finite-state machines and timed circuits designed using a variety of timing models. Cyclic paths, pulse generating paths, and unbounded length self-enabling loops are identified inside these circuit blocks. Some of the causal paths in these designs have never been previously identified. No preliminary versions of this work have been previously published.

Crosstalk Reduction on Delay Line with Rectangular-Patches (RPs) Design

In this paper, a novel helix delay line with RPs structures is proposed to investigate the performance of crosstalk reduction. In the past, conventional delay lines consist of equal-length parallel unit lines which are closely packed to minimize the fabricated cost and routing area. All spacing between the adjacent parallel unit lines of delay lines should be smaller. When the operating signal frequency ups to the GHz level, the electromagnetic noise has become a dominant issue coupling from adjacent lines. It is called as a crosstalk source. The crosstalk may affect system-level timing. Besides, it causes error switching of logic gates that will reduce the signal quality. The feature of proposed helix delay line is that the far-end crosstalk (FEXT) is a dominated noise that accumulates at the receiving end. RPs structures are added and aligned at the center of the two parallel adjacent unit lines of the proposed helix delay line, which are used to reduce the difference between inductive and capacitive coupling coefficient ratios, and to reduce FEXT that maintains the signal integrity (SI) quality on receiving end.

Timestamp-Free Clock Syntonization for IoT Using Carrier Frequency Offset

System-level timing fluctuations caused by unstable low-cost clocks and end-to-end communication delays are the main sources of uncertainties in existing synchronization mechanisms that rely on timestamp exchanges. This paper introduces a timestamp-free clock syntonization approach, carrier frequency offset (CFO)-assisted syntonization (CFOSynt), to estimate the clock skew between a pair of nodes by utilizing carrier frequency offset. To enable CFOSynt, we leverage the fact that RF oscillators in the radio can be used as the reference to calibrate the system clock oscillators, and the pairwise RF clock information is carried in the transmission carrier frequency. By incorporating CFO and capturing the clock frequency relationship in system clock skew estimation, CFOSynt can eliminate the need for timestamping and the impact of delay uncertainties. To validate the design, CFOSynt is implemented on two common off-the-shelf (COTS) IoT platforms with access to the CFO estimation from the radio chip. Extensive experiments are conducted to evaluate CFOSynt, and CFOSynt can estimate the clock skew of 32 kHz low-cost electronic oscillators with a mean error of -2.46 Hz. In comparison with timestamp-based approaches, CFOSynt achieves up to 70-90% improvement in skew estimation error and shows significant reliability when low-cost oscillators are used.

Fundamental limitations of spectrally-sliced optically enabled data converters arising from MLL timing jitter.

The effect of phase noise introduced by optical sources in spectrally-sliced optically enabled DACs and ADCs is modeled and analyzed in detail. In both data converter architectures, a mode-locked laser is assumed to provide an optical comb whose lines are used to either synthesize or analyze individual spectral slices. While the optical phase noise of the central MLL line as well as of other optical carriers used in the analyzed system architectures have a minor impact on the system performance, the RF phase noise of the MLL fundamentally limits it. In particular, the corresponding jitter of the MLL pulse train is transferred almost one-to-one to the system-level timing jitter of the data converters. While MLL phase noise can in principle be tracked and removed by electronic signal processing, this results in electric oscillator phase noise replacing the MLL jitter and is not conducive in systems leveraging the ultra-low jitter of low-noise mode-locked lasers. Precise analytical models are derived and validated by detailed numerical simulations.

A Timed-Value Stream Based ESL Timing and Power Estimation and Simulation Framework for Heterogeneous MPSoCs

Consideration of an embedded system’s timing behavior and power consumption at system-level is an ambitious task. Sophisticated tools and techniques exist for power and timing estimations of individual components such as custom hard- and software as well as IP components. In this article we present an ESL framework for timing and power aware virtual system prototyping of heterogeneous MPSoCs consisting of software, custom hardware and 3rd party IP components. In virtual platform, previously only used for functional software verification, our proposed timed value streams enable a hierarchical and composable power model. Our proposed ESL framework supports the integration of a broad range of system-level timing and power models into virtual platform. Power and timing models can either be generated from a functional C/C++ description or include state-machine based power models to existing functional and timed virtual platform (black-box) components. Our timed value stream based power model supports the run-time analysis of different platform power management strategies with configurable temporal abstraction, supporting simulation speed and accuracy trade-offs. This work evaluates timing and power back-annotation and power state machine based approaches with timed value streams in two use-cases: An MP3 decoder, compared to a power-aware ISS and gate-level simulation, and an FPGA based many-core architecture against measurements. Finally, the simulation time overhead of the proposed stream based power model is analyzed and discussed.

Synthesis of Monitors for Networked Systems With Heterogeneous Safety Requirements

Complex embedded systems such as automobiles and IoT-systems feature a wide range of applications with varying degrees of safety relevance. As many applications on these devices interlace more and more, new ways to guarantee sufficient isolation between safety levels become necessary. Previous work only regarded monitoring of timing properties for individual tasks on single resources and neglected functional cause-effect chains. This makes their application costly because nearly every task would require monitoring due to unknown system-level timing dependencies. We present cross-layer dependency analysis of timing properties and system-level synthesis strategies for monitors utilizing a reachability formulation of the problem. Our approach regards distributed cause-effect chains on networked platforms for which the accuracy of timing parameters can vary and heterogeneous safety requirements can be specified.

The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

The consideration of an embedded device’s power consumption and its management is increasingly important nowadays. Currently, it is not easily possible to integrate power information already during the platform exploration phase. In this paper, we discuss the design challenges of today’s heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators.As a result, we propose a reference framework and design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alternatives, and power management strategies.Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. We propose an efficient code annotation technique for timing and power properties enabling fast host execution as well as adaptive collection of power traces. Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off analysis between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed framework and design flow has been implemented in the COMPLEX FP7 European integrated project.

Polychronous modeling, analysis, verification and simulation for timed software architectures

High-level modeling languages and standards, such as Simulink, SysML, MARTE and AADL (Architecture Analysis & Design Language), are increasingly adopted in the design of embedded systems so that system-level analysis, verification and validation (VV an original clock-based timing analysis and validation of the overall system is achieved via a formal polychronous/multi-clock model of computation. In order to avoid semantics ambiguities of AADL and Simulink, their features related to real-time and logical time properties are first studied. We then endue them with a semantics in the polychronous model of computation. We use this model of computation to jointly analyze the non-functional real-time and logical-time properties of the system (by means of logical and affine clock relations). Our approach demonstrates, through several case-studies conducted with Airbus and C-S Toulouse in the European projects CESAR and OPEES, how to cope with the system-level timing verification and validation of high-level AADL and Simulink components in the framework of Polychrony, a synchronous modeling framework dedicated to the design of safety-critical embedded systems.

Fast timing analysis of clock networks considering environmental uncertainty

Dynamic power management can significantly introduce environmental uncertainties such as non-uniform temperature gradients and supply voltage fluctuations. This can bring many challenges for the system-level timing verification such as for global clock networks. This paper presents a fast verification of clock-skew by an incremental-SVD-based compact modeling assisted with adaptive sampling. Firstly, an incremental-SVD is developed to perform an efficient update of environmental uncertainties avoiding a repeated full SVD. Secondly, an adaptive sampling is presented to build accurate models to sample clock and clock-skew for generating macromodels in a wide frequency range. Experiments on a number of clock networks show that when compared to the traditional fast TBR method, our macromodeling by incremental-SVD and adaptive sampling can significantly reduce the runtime with a similar accuracy. In addition, when compared to the Krylov-subspace-based method, our macromodeling further reduces the waveform error with a similar runtime.

The Analysis of System-Level Timing Failures Due to Interconnect Reliability Degradation

The continuous scaling of feature dimensions and the introduction of new dielectric materials are pushing interconnects closer to their reliability limits. Degradation mechanisms are becoming more pronounced, making the interconnect lifetime a challenge at the level of process qualification. Moreover, these mechanisms exhibit new properties, such as gradual degradation of electrical parameters instead of abrupt breakdown phenomena. As a result, it becomes more likely that systems will fail because one of their transistors or wires becomes gradually too slow. These soft failures are not captured by existing tools. The methodology introduced in this paper estimates the impact of two dominant interconnect degradation mechanisms (electromigration and time-dependent dielectric breakdown) on the total system performance. This constitutes a first step toward system-level-driven reliability-aware design for interconnects.

Timed Behavior Trees for Failure Mode and Effects Analysis of time-critical systems

Behavior Trees are a graphical notation used for formalising functional requirements, and have been successfully applied to several industrial case studies. However, the standard notation does not support the concept of time, and consequently its application is limited to non-real-time systems. To overcome this limitation we extend the notation to timed Behavior Trees. We provide an operational semantics which is based on timed automata, and thus serves as a formal basis for the translation of timed Behavior Trees into the input notation of the timed model checker UPPAAL. System-level timing properties of a Behavior Tree model can then be automatically verified using UPPAAL. Based on the notational extensions with model checking support, we introduce timed Failure Mode and Effects Analysis, a process for identifying cause-consequence relationships between component failures and system hazards in real-time safety critical systems.

Process-Driven Variability Analysis of Single and Multiple Voltage–Frequency Island Latency-Constrained Systems

The problem of determining bounds for application completion times running on generic systems comprising single or multiple voltage-frequency islands (VFIs) with arbitrary topologies is addressed in the context of manufacturing-process-driven variability. The approach provides an exact solution for the system-level timing yield in synchronous single-voltage (SSV) and VFI systems with an underlying tree-based topology and a tight upper bound for generic non-tree-based topologies. The results show that: 1) timing yield for the overall source-to-sink completion time for generic systems can be modeled in an exact manner for both SSV and VFI systems and 2) multiple-VFI latency-constrained systems can achieve up to two times higher timing yield than their SSV counterparts. The results are formally proven and are supported by experimental results on two embedded applications, namely, a software-defined radio and a Moving Pictures Expert Group 2 encoder.

Phase Locked System Design and Measurement Tutorial Consisting of Physical Hardware and Co-Simulation Environment

Phase locked loop based feedback techniques are used in a variety of system level timing, control and communication applications. Re-configurable hardware and associated simulation models have been developed with an emphasis towards teaching the fundamentals of phase locked loop systems. The material is hardware focussed and reinforces control system theory, characterisation, design, and modelling. The simulation part of the material can be used in an Internet based teaching environment.

End-to-end design of distributed real-time systems

This paper presents a systematic approach to the design of distributed real-time systems with system-level timing requirements. It is often extremely difficult to design such a system in a composable fashion, since temporal relationships induced by system-level timing requirements introduce complicated couplings between structurally irrelevant components. As a solution to this problem, the approach described here maps system-level timing requirements onto component-level timing constraints. More specifically, it first transforms system-level requirements into a set of non-linear intermediate constraints; and then derives task attributes such as periods, phases, and deadlines, with the objective of maximizing the chances of the system being schedulable. The final results preserve the desired timing correctness: if the final task set is schedulable, then the original system-level requirements will be satisfied. The approach is demonstrated and experimentally validated via an example of a numerical control system built on the FIP network.

MIS: A Multiple-Level Logic Optimization System

MIS is both an interactive and a batch-oriented multilevel logic synthesis and minimization system. MIS starts from the combinational logic extracted, typically, from a high-level description of a macrocell. It produces a multilevel set of optimized logic equations preserving the input-output behavior. The system includes both fast and slower (but more optimal) versions of algorithms for minimizing the area, and global timing optimization algorithms to meet system-level timing constraints. This paper provides an overview of the system and a description of the algorithms used. Included are some examples illustrating an input language used for specifying logic and don't-cares. Parts on an industrial chip have been re-synthesized using MIS with favorable results as compared to equivalent manual designs.