System-level Performance Metrics Research Articles

Application-Based Congestion Control Policy for the Communication Channel in VANETs

This letter proposes a novel proactive congestion control policy for vehicular ad-hoc networks, in which each vehicle's communication parameters are adapted based on their individual application requirements. Contrary to other approaches, where transmission resources tend to be assigned based on system-level performance metrics, the technique proposed in this paper aims to individually satisfy the target application performance of each vehicle, while globally minimising the channel load to prevent channel congestion.

An Experimental Evaluation of the HP V-Class and SGI Origin 2000 Multiprocessors using Microbenchmarks and Scientific Applications

As processor technology continues to advance at a rapid pace, the principal performance bottleneck of shared memory systems has become the memory access latency. In order to understand the effects of cache and memory hierarchy on system latencies, performance analysts perform benchmark analysis on existing multiprocessors. In this study, we present a detailed comparison of two architectures, the HP V-Class and the SGI Origin 2000. Our goal is to compare and contrast design techniques used in these multiprocessors. We present the impact of processor design, cache/memory hierarchies and coherence protocol optimizations on the memory system performance of these multiprocessors. We also study the effect of parallelism overheads such as process creation and synchronization on the user-level performance of these multiprocessors. Our experimental methodology uses microbenchmarks as well as scientific applications to characterize the user-level performance. Our microbenchmark results show the impact of L1/L2 cache size and TLB size on uniprocessor load/store latencies, the effect of coherence protocol design/optimizations and data sharing patterns on multiprocessor memory access latencies and finally the overhead of parallelism. Our application-based evaluation shows the impact of problem size, dominant sharing patterns and number of processors used on speedup and raw execution time. Finally, we use hardware counter measurements to study the correlation of system-level performance metrics and the application's execution time performance.

Design of High-Performance System-On-Chips Using Communication Architecture Tuners

In this paper, we present a methodology for the design of high-performance system-on-chip communication architectures. The approach is based on the addition of a layer of circuitry called the communication architecture tuner (CAT) layer around an existing communication architecture topology. The added layer provides a system with the capability of adapting to runtime variability in the communication needs of its constituent components. For example, more critical data may be handled differently, leading to lower communication latencies. The CAT associated with each component monitors its internal state, analyzes the communication transactions it generates, and predicts the relative importance of the transactions in terms of their impact on system-level performance metrics. It then configures the protocol parameters of the underlying communication architecture (e.g., priorities, burst modes, etc.) to best suit the system's changing communication needs. We illustrate the issues and tradeoffs involved in the design of CAT-based communication architectures, and present algorithms that automate the key steps. Experiments with example systems indicate that performance metrics (e.g., number of missed deadlines, average processing time) for systems with CAT-based communication architectures are significantly (sometimes over an order of magnitude) better than those with conventional communication architectures.

Active inlet flow control technology demonstration

AbstractThis paper presents results from a joint Lockheed Martin/NASA Glenn effort to design and verify an ultra-compact, highly-survivable engine inlet subsonic duct based on the emerging technology of active inlet flow control (AIFC). In the AIFC concept, micro-scale actuation (∼mm in size) is used in an approach denoted ‘secondary flow control’ to intelligently alter a serpentine duct's inherent secondary flow characteristics with the goal of simultaneously improving the critical system-level performance metrics of total pressure recovery, spatial distortion, and RMS turbulence. In this approach, separation control is a secondary benefit, not a design requirement. The baseline concept for this study was a 4:1 aspect ratio ultra-compact (LID= 2·5) serpentine duct that fully obscured line-of-sight view of the engine face. At relevant flow conditions, this type of duct exhibits excessive pressure loss and distortion because of extreme wall curvature. Two sets of flow control effectors were designed with the intent of establishing high performance levels to the baseline duct. The first set used two arrays of 36 co-rotating microvane vortex generators (VGs); the second set used two arrays of 36 micro air-jet (microjet) VGs, which were designed to produce the same ‘vorticity signature’ as the microvanes. Optimisation of the microvane array was accomplished using a design of experiments (DOE) methodology to guide selection of parameters used in multiple Computational Fluid Dynamics (CFD) flow solutions. A verification test conducted in the NASA Glenn W1B test facility indicated low pressure recovery and high distortion for the baseline duct without flow control. With microvane flow control, at a throat Mach number of 0·60, pressure recovery was increased 5%, and both spatial distortion and turbulence were decreased approximately 50%. Microjet effectors also provided significantly improved performance over the baseline configuration.