Synthesis Of Finite State Machines Research Articles

TEST GRAPH-SCHEMES OF THE ALGORITHMS OF FINITE STATE MACHINES WORK FOR ASSESSING THE EFFICIENCY OF AUTOMATED SYNTHESIS IN XILINX VIVADO CAD

Context. The problem of evaluating the effectiveness of the automated design of a microprogram finite state machine with the operational transformation of state codes using Xilinx Vivado CAD is considered. The object of the research was graph-schemes of control algorithms implemented by finite state machine and able to prove the effectiveness of the principle of operational transformation of state codes in comparison with standard synthesis methods built into the CAD, in the context of hardware expenses optimization.
 Objective. Development and research of graph-schemes of control algorithms in order to substantiate the effectiveness of the application of structure of the finite state machine with datapath of transitions in comparison with the built-in methods of synthesizing finite state machines in Xilinx Vivado CAD in the basis of programmable logic devices.
 Method. The research is based on the hypothetical assumption that the Xilinx Vivado CAD has built-in methods of automated design of the circuit of a finite state machine, the effectiveness of which, according to the criterion of hardware expenses, exceeds other known methods of optimizing hardware expenses in the finite state machine circuit. In order to refute this hypothesis, it is proposed to prove that in some cases known methods of hardware expenses optimization in the finite state machine circuit are more effective in comparison with the methods built into CAD. In this work, as a well-known optimization method, the method of operational transformation of state codes, which corresponds to the structure of a finite state machine with datapath of transitions, is chosen. The effectiveness of this method is demonstrated on the example of several test graph-schemes of algorithms, the structure of which is abstract and artificially adapted to the chosen optimization method. The adaptation of the selected graph-schemes of the algorithms consists in the fact that a relatively small number of transition operations is required for their implementation with the help of a finite state machine with datapath of transitions. This contributes to the simplification of the circuit of the finite state machine and the reduction of hardware costs for its implementation. At the same time, the test graph-schemes of the algorithms have the possibility of scaling, which allows to automate the construction of VHDL models of the corresponding finite state machines for graph-schemes of different sizes and to evaluate the optimization of hardware expenses for finite state machines of different complexity.
 Results. Using the example of several graph-schemes of algorithms, it is demonstrated that in some cases none of the finite state machine synthesis methods built into the Xilinx Vivado CAD is able to surpass the method of operational transformation of state codes according to the criterion of hardware expenses for the implementation of a finite state machine circuit. At the same time, a several-fold gain in hardware expenses can be achieved, which indicates the expediency of using this method under certain conditions. The formal definition of such conditions for the considered and other known optimization methods is a separate unsolved scientific problem.
 Conclusions. The conducted experiments confirmed that in some cases, the known methods of synthesis of finite state machines allow to obtain circuits with lower hardware expenses than when using the methods of synthesis of finite state machines contained in Xilinx Vivado CAD. This testifies to the general expediency of using existing and developing new methods of hardware expenses optimization in the circuit of the finite state machines and the current relevance of the theory of the synthesis of digital automata as a scientific direction.

SYNTHESIS OF THE FINITE STATE MACHINE WITH DATAPATH OF TRANSITIONS ACCORDING TO THE OPERATIONAL TABLE OF TRANSITIONS

Context. The problem of formalizing the description of a microprogram finite state machine based on the principle of operational transformation of state codes with the help of a modified transition table is considered. The object of research was a model of a microprogram finite state machine with datapath of transitions.
 Objective. The goal of the work is development and research of a method for formally specifying a microprogram finite state machine with datapath of transitions in the form of a modified table of transitions containing sufficient information for synthesizing the logic circuit of the finite state machine in the basis of programmable logic devices.
 Method. A new way of representing the formal solution of the problem of algebraic synthesis of a microprogram finite state machine with datapath of transitions in the form of an operational table of transitions is proposed. This table is a modification of the direct structural table traditionally used in the synthesis of microprogram finite state machines. The use of the previously known representation of the formal solution of the problem of algebraic synthesis in the form of a system of isomorphisms of automaton algebras is too formalized and makes it difficult to synthesize the logical circuit of the finite state machine due to the separate description of the transition and output functions. It is shown that the structure of a microprogram finite state machine with datapath of transitions requires information about the set of interpretations of state codes and the transition operations used to be entered into the traditional table of transitions. It is noted that the proposed operational table of transitions contains sufficient information for the synthesis of the logical circuit of the finite state machine. An example of constructing an operational table of transitions for a finite state machine given by a graph-scheme of the implemented control algorithm is shown. The example demonstrates various ways to interpret state codes. The procedure for synthesizing the circuit for generating codes of transition operations and the circuit for generating microoperations according to the operational table of transitions is proposed.
 Results. An example of the implementation of the main stages of the synthesis of a finite state machine with datapath of transitions according to the operational table of transitions is considered. Examples of synthesized finite state machine models in the VHDL language are given, which take into account the peculiarities of the representation of finite state machine models in Xilinx Vivado CAD. The results of the synthesis of the finite state machine according to VHDL models in FPGA basis are shown.
 Conclusions. The experiments carried out confirmed the sufficiency of the operational table of transitions for describing a microprogram finite state machine with operational transformation of state codes for the purpose of further synthesizing its logic circuit. Prospects for further research are the use of the proposed operational table of transitions in the development of various methods for the synthesis and optimization of microprogram finite state machine with operational transformation of state codes.

Optimization of a Moore Automaton Circuit in a Mixed Element Basis

Introduction. The control unit is one of the most important building blocks of any digital system. The main function of the control unit is to coordinate the interaction between all system blocks. Therefore, the characteristics of a control unit circuit have a significant impact on the quality of the system as a whole. To represent the law of functioning of a control unit, the models of the Moore and Mealy finite state machines (FSM) are used. When synthesizing circuits of FSMs, it is necessary to solve a number of optimization problems, such as the reducing hardware amount, increasing performance, minimizing power consumption, joint optimization of hardware-temporal characteristics. Methods for solving these problems largely depend on the used logical elements. Currently, FPGA microchips are one of the main platforms in which modern digital systems are implemented. The main blocks in the FPGA, which are used in the implementation of FSM circuits, are embedded memory blocks (EMBs), logical blocks LUT (look-up table) and a system of programmable interconnections. The best characteristics are possessed by FSM circuits implemented with EMBs. However, EMBs are widely used to implement various operational blocks of digital systems. Therefore, the designer of a control unit circuitry can use a rather limited number of EMBs. Purpose of the article. The article deals with the extreme case when there is only a single "free" EMB available. In this case, the FSM circuit is represented by a network consisting of this EMB and LUTs. There is proposed a method for the synthesis of an FSM with the optimization of the number of LUTs, when only one EMB block is available for implementing some part of the circuit. The proposed method is based on the using classes of pseudoequivalent states of Moore FSMs. The states are coded in such a way that the state code consists of the code of the class of pseudoequivalent states and the code of a collection of microoperations. Results. Studies of the effectiveness of the proposed method were carried out on standard FSMs. FPGAs of the Virtex-7 family from Xilinx were used as an implementation platform. The research results showed that the proposed method allows reducing the number of LUTs in FSM circuits by 12 % – 19 % in comparison with the known methods. In all cases, only a single EMB was used. Conclusions. The effectiveness of the proposed method allows us to recommend it for use in the synthesis of FSMs if there is of an extreme shortage of EMBs. Keywords: Moore FSM, FPGA, LUT, EMB, pseudoequivalent states, synthesis.

Synthesis of Fast Finite State Machines on Programmable Logic Integrated Circuits by Splitting Internal States

Synthesis of Fast Finite State Machines on Programmable Logic Integrated Circuits by Splitting Internal States

Low power transistor level synthesis of finite state machines using a novel dual gating technique

Low power transistor level synthesis of finite state machines using a novel dual gating technique

Low power transistor level synthesis of finite state machines using a novel dual gating technique

In this work, an efficient technique of clock and power gating is concurrently introduced in finite state machines (FSM) with a view to minimising the overall power dissipation. The proposed power gating concept works on the principle of shutting down the power supply to the FSM during periods of inactivity. The extraction of the inactivity criteria is based on the occurrence of self-loops within the FSM or an unchanged FSM output between successive clock pulses. Clock gating, on the other hand, disables the clock signal to the sequential blocks of the FSM during this inactive/idle periods. The idea of implementing the gating in both the state logic as well as output logic is introduced in this work. The proposed approach has been introduced in three benchmark FSM circuits, simulated and synthesised in Cadence digital design tool. The results indicate a maximum of 73% total power savings (dynamic and static) with an average penalty of 27% area (approx.).

Sequential algorithm for low-power encoding internal states of finite state machines

A heuristic method for encoding internal states (state assignment) of finite state machines (FSMs) so as to reduce their power consumption is proposed. A feature of the proposed approach is that the state assignment procedure takes into account the activity function of the memory elements when the FSM transits from a current state to other states that have already been encoded. A procedure for determining the power consumption of the FSM based on the codes of its internal states and probabilities of appearance of units at each input of the FSM is described. Experiments showed that the proposed approach makes it possible to reduce the power consumption of the FSM by 39% on the average compared with the NOVA algorithm and sometimes by 68%. In conclusion, the possibilities of improving the performance of the proposed algorithm in the synthesis of a specific FSM are discussed and promising directions of further research are indicated.

Implementation of finite-state machines based on programmable logic ICs with the help of the merged model of Mealy and Moore machines

The problem concerning the synthesis of finite-state machines (FSMs) based on programmable logic ICs, in which FSM’s output variables serve as the code (or part of the code) of internal states, has been examined. A solution to the problem is obtained with the help of the merged model of Mealy and Moore machines. A principal distinction between the proposed and well-known techniques is that an initial FSM undergoes no conversions related to an increase in the number of internal states and transitions thereof. The necessary conditions under which output variables can be used as the code of FSM’s internal states are presented. The method for synthesizing the merged model AC of Mealy and Moore machines is described. Basic results of investigations, as well as promising directions of further studies concerned with the development of new structural models of FSMs, are discussed.

Synthesis of finite state machines for CPLDs

Synthesis of finite state machines for CPLDsThe paper presents a new two-step approach to FSM synthesis for PAL-based CPLDs that strives to find an optimum fit of an FSM to the structure of the CPLD. The first step, the original state assignment method, includes techniques of two-level minimization and aims at area minimization. The second step, PAL-oriented multi-level optimization, is a search for implicants that can be shared by several functions. It is based on the graph of outputs. Results of experiments prove that the presented approach is especially effective for PAL-based CPLD structures containing a low number of product terms.

Synthesis of finite state machines for improved state verification

Finite State Machines (FSMs) are used in diverse areas to model hardware and software systems. Verification of FSMs is essential to ensure reliability of systems. To verify that a machine is in an expected state in testing, Unique Input/Output (UIO) sequences are used. The aforementioned testing methodology requires that each state in the FSM has an UIO. However, it is possible for a given machine that few or even none of its states have an UIO sequence. This paper presents a guided heuristic algorithm for synthesizing FSMs such that each state has an UIO sequence. The states of an FSM with identical I/O labels on transitions are grouped in order to identify the states which do not possess UIO sequence. The transitions are then augmented by adding extra output terminals incrementally so that new UIO sequences are created for the states. A greedy approach is used to optimize the number of added outputs. Initially, the transitions which lead to state convergence (i.e., transitions with identical input/output labels taking a set of states to the same next state) and constrained self-loop (i.e., transitions taking a set of states either to itself or leads to state convergence) are identified since a state with only these transitions will never have a UIO sequence. Extra output terminals are added to the FSM which are used only while testing and the augmented output labels make sure that the states are neither convergent nor has constrained self-loop, thereby ensuring UIO sequence. The proposed algorithm, referred to as AUGP, was tested with a large number of FSMs including the Microelectronics Center of North Carolina (MCNC) FSM benchmarks. The augmented state transition table was used as input to a UIO computation algorithm (developed by the same authors [Ahmad I, et al. IEE Proc Comput Digital Tech 2004;151(2):131]) to check the performance of the augmentation algorithm and the tested FSMs were found to possess UIO sequence for all states.

B01: The novel approach to FSM synthesis targeted FPGA architectures

This paper presents the novel approach to logic synthesis of finite state machines for FPGA architectures. Traditional methods are based on two steps: internal states encoding and then mapping of encoded state transition table into target architecture. In case of FPGAs the functional decomposition is recognized as the most efficient method of digital circuits’ implementation. However none of known state encoding algorithms can be considered as the best method to be used with the functional decomposition. In this paper the concept of symbolic functional decomposition is introduced. In this method no separate encoding step is required. Symbolic functional decomposition accepts FSM with symbolic states and performs decomposition introducing such state encoding that guarantees the best solution.

Partitioning based Approach for Finite State Machine State Encoding Targeting Low Power

State encoding is one of the most crucial steps in the synthesis of finite state machines. Due to the enhanced emphasis on low power circuit design, state encoding strategies targeting low power consumption are sought after. Other approaches try to solve the problem by partitioning the FSM into two sub-FSMs, -this generally require larger register area. This paper utilizes the concept of state partitioning to solve the state-encoding problem. Experimental results show that even without physically partitioning the FSM into sub-FSMs, the scheme results in 48.89% power reduction over NOVA [1] and 26.64% lesser power than GA-D [2] which is directed towards low power state encoding.

Synthesis of Synchronous Finite State Machines for All-Optical Implementations

In this paper an efficient method to synthesize all-optical synchronous digital finite state machines is suggested. The synthesis is based on the design of purely combinational circuits composed of a cascade of iterative cells that perform the same logical functions of the corresponding synchronous Finite State Machine (FSM). This allows high bit rates and a high degree of modularity, so an easy integration of the circuit is possible. These characteristics make the method suitable to be adopted in a photonic environment in which clocked digital memory elements are still a critical aspect.

An integrated state assignment and flip-flop selection technique for FSM synthesis

In the automatic synthesis of Finite State Machines (FSMs), the state assignment and the choice of flip-flops significantly affect the cost of the combinational logic. To meet the demands of the increasing complexity of integrated circuits, we present an integrated state assignment and sequential element selection approach to synthesize area-efficient FSMs. The FSM synthesis approach is modeled as an optimization problem and is solved by using the guided evolutionary simulated annealing (GESA) technique. The GESA is a new type of parallel and distributed processing approach for searching the optimal solutions. Since the optimization problem at hand is NP-hard, a distributed algorithm for the GESA technique is developed and implemented on Network of Workstations (NOW) to speedup the search process. Promising speedups are obtained by running the distributed GESA algorithm on a NOW. Efficacy of the proposed technique is demonstrated by carrying out a comparison with other state-of-the-art techniques such as the MUSTANG, NOVA and JEDI for MCNC benchmarks. The proposed integrated state assignment and sequential element selection approach allows all types of flip-flops and offers considerable improvement in PLA area as compared to the existing techniques that use only D type flip-flops as the sequential element.

Generating FSMs from interworkings

A technique for the automated synthesis of FSMs (finite state machines) from sets of interworkings (synchronous sequence charts) is described. This is useful for obtaining feedback from a set of scenarios during a system's definition phase or test phase. It is sound in the sense that the generated FSM only exhibits traces that correspond to one of the interworkings from the given set. It preserves deadlock freedom in the sense that no behaviours are lost. The concrete syntax of SDL is used to represent the resulting FSMs.

On the synthesis of synchronizable finite state machines with partial scan

On the synthesis of synchronizable finite state machines with partial scan

Embedding large finite state machines into programmable devices

There exist powerful CAD tools for the automated synthesis and implementation of finite state machines (FSMs). Programmable logic devices (PLDs) have a short time to market, thus they are widely used for the realization of FSMs. The use of conventional design tools yields results that are often suboptimal because the synthesis tools often do not consider the soecial structure of PLDs. This paper deals with embedding problems of large FSMs into PLDs. It will be shown how the normally inexact specification, an adapted state-coding, as well as well-considered decomposition of large designs, and the choice of the optimal flip-flop type may be used to embed large designs into a minimal number of PLDs.

CLASS: a CAD system for automatic synthesis and verification of asynchronous finite state machines

This paper describes algorithms and techniques underlying a CAD system called CLASS (Cirrus Logic Asynchronous Synthesis System) for automatic synthesis and verification of control circuits based on Asynchronous Finite State Machine (AFSM) specifications. AFSM specifications are transformed into Signal Transition Graphs, and then to State Graphs. Newly developed hazard-free synthesis techniques from State Graphs will be described. An efficient two-level hierarchical verification technique based on State Graph Contraction and Dill's verifier is used to verify the logic implementations against the state graph.

On the Synthesis of Finite-State Machines from Samples of Their Behavior

The Nerode realization technique for synthesizing finite-state machines from their associated right-invariant equivalence relations is modified to give a method for synthesizing machines from finite subsets of their input?output behavior. The synthesis procedure includes a parameter that one may adjust to obtain machines that represent the desired behavior with varying degrees of accuracy and that consequently have varying complexities. We discuss some of the uses of the method, including an application to a sequential learning problem.

Amendments to Zeiger's cascade synthesis of finite-state machines

Zeiger 1967 details a procedure for decomposing a finite automaton into a cascade of permutation-reset machines. Therein are several errors and an ambiguity in the steps for making next-state assignments in the machines of the cascade. Several of the necessary adjustments appeared in the errata published on page 471, Volume 11, of this journal. The present work suggests further modifications, subsuming some of those which appeared earlier.