Abstract
This paper describes algorithms and techniques underlying a CAD system called CLASS (Cirrus Logic Asynchronous Synthesis System) for automatic synthesis and verification of control circuits based on Asynchronous Finite State Machine (AFSM) specifications. AFSM specifications are transformed into Signal Transition Graphs, and then to State Graphs. Newly developed hazard-free synthesis techniques from State Graphs will be described. An efficient two-level hierarchical verification technique based on State Graph Contraction and Dill's verifier is used to verify the logic implementations against the state graph.
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