Synthesis Of Combinational Logic Circuits Research Articles

Experimental Comparison of Logic Circuit Synthesis Methods

This paper presents the results of an experimental comparison of methods for the synthesis of combinational logic circuits that implement specified Boolean functions. The following methods were considered: the method of Akers, bi-decomposition, the methods of cascades, Minato-Morreale, Reed-Muller and DSD-decomposition. The comparison was based on an estimate of power, delay and area of synthesized logic circuits. The evaluation was carried out without the process of technology mapping of the circuits. These parameters were chosen because they are the main criteria for technology-independent optimization, where these methods are widely used. Boolean functions with the number of arguments from 4 to 10 were used as input data. They were generated on the basis of information on the frequency of occurrence of various NPN-equivalence classes of Boolean functions of 4 variables. As a result of the study, it was found that the Minato-Morreale method is the most universal in solving technology-independent optimization problems and can be used for different criteria.

Virtual reconfigurable architecture for evolving combinational logic circuits

A virtual reconfigurable architecture (VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level. The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect (PCI) board with an Xilinx Virtex xcv2000E field programmable gate array (FPGA). To improve the quality of the evolved circuits, the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit. To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning, a self-adaptive mutation rate control (SAMRC) scheme is introduced. In the evolutionary process, the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations. The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function, a 2-bit multiplier, and a 3-bit multiplier. The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort, when compared to the existing evolvable hardware approaches.

Crossing genetic and swarm intelligence algorithms to generate logic circuits

Genetic Algorithms (GAs) are adaptive heuristic search algorithm based on the evolutionary ideas of natural selection and genetic. The basic concept of GAs is designed to simulate processes in natural system necessary for evolution, specifically those that follow the principles first laid down by Charles Darwin of survival of the fittest. On the other hand, Particle swarm optimization (PSO) is a population based stochastic optimization technique inspired by social behavior of bird flocking or fish schooling. PSO shares many similarities with evolutionary computation techniques such as GAs. The system is initialized with a population of random solutions and searches for optima by updating generations. However, unlike GA, PSO has no evolution operators such as crossover and mutation. In PSO, the potential solutions, called particles, fly through the problem space by following the current optimum particles. PSO is attractive because there are few parameters to adjust. This paper presents hybridization between a GA algorithm and a PSO algorithm (crossing the two algorithms). The resulting algorithm is applied to the synthesis of combinational logic circuits. With this combination is possible to take advantage of the best features of each particular algorithm.

Evolutionary design of combinational logic circuits using VRA processor

This paper presents a virtual reconfigurable architecture (VRA)-based evolvable hardware for automatic synthesis of combinational logic circuits. The VRA processor is implemented on a Xilinx FPGA and works through two-stage evolutions: (1) finding a functional circuit, and (2) minimizing the number of gates used. To optimize the algorithm performance in the evolutionary process, a self-adaptive mutation rate control scheme is introduced. The efficiency of the proposed methodology is tested with the evolution of a 3-bit multiplier. The obtained results demonstrate that our approach improves the evolutionary design of electronic circuits in terms of quality of the evolved circuit as well as the computational effort.

Computational Intelligence in Circuit Synthesis

This paper is devoted to the synthesis of combinational logic circuits through computational intelligence or, more precisely, using evolutionary computation techniques. Are studied two evolutionary algorithms, the Genetic and the Memetic Algorithm (GAs, MAs) and one swarm intelligence algorithm, the Particle Swarm Optimization (PSO). GAs are optimization and search techniques based on the principles of genetics and natural selection. MAs are evolutionary algorithms that include a stage of individual optimization as part of its search strategy, being the individual optimization in the form of a local search. The PSO is a population-based search algorithm that starts with a population of random solutions called particles. This paper presents the results for digital circuits design using the three above algorithms. The results show the statistical characteristics of this algorithms with respect to the number of generations required to achieve the solutions. The article analyzes also a new fitness function that includes an error discontinuity measure, which demonstrated to improve significantly the performance of the algorithm.

An efficient algorithm for constrained encoding and its applications

An efficient algorithm and its implementation, ENCORE, are presented for finding approximate solutions to dichotomy-based constrained encoding, a problem fundamental to the synthesis of combinational logic circuits, and synchronous and asynchronous sequential circuits. ENCORE adopts a greedy strategy to find an encoding bit by bit, and then uses an iterative method to improve the solution quality. The novelty of the algorithm lies mainly in a linear-time heuristic to select each individual bit; this problem was previously solved in quadratic time. ENCORE has been applied to a variety of practical problem instances. For a number of examples found in the literature on the synthesis of asynchronous sequential machines, ENCORE consistently obtains optimal or near-optimal results. For the optimum state assignment of the MCNC FSM benchmarks, ENCORE generates the same or even shorter encoding lengths than the programs KISS, NOVA and DIET, but takes much less CPU time. It is demonstrated for the first time that PLA implementations of synchronous FSMs using dichotomy constraints compare very favorably with respect to area with those based on traditional group constraints.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An Approach to Unified Methodology of Combinational Switching Circuits

A methodology based on the theory of Boolean equations has been developed which permits a unified approach to the analysis and synthesis of combinational logic circuits. The type of circuits covered by the approach includes both the classical loopless combinational networks as well as those that contain closed feedback loops and thus have internally a sequential character. To that end, a general multiple-output circuit represented by a Mealy-type machine is studied using characteristic equations (functions) that describe its internal structure. It is shown how behavioral properties of the circuit are reflected through the sosutions of these equations. Moreover, it is demonstrated that a multiple-output incompletely specified switching function is reaeized if a ≤ relation is satisfied between the corresponding charchteristic functions. This leads to a new unified outlook on functional decomposition as used in modular synthesis procedures. Although the building modules are allowed to be sequential circuits, it is shown under which conditions the feedback loops are redundant with respect to the realization of a given output characteristic function, and thus the existence conditions of nondegenerate combinational circuits with loops are stated.

The H Diagram: A Graphical Approach to Logic Design

A geometric model, termed an H diagram, is an effective visual aid in the synthesis of combinational logic circuits. The model is derived by means of coordinate transformations of a hypercube, resulting in a simple two-dimensional framework for mapping a binary function. The H diagram can be expanded to accommodate an arbitrary number of variables, while maintaining a mathematically consistent pattern that permits the extension of simple geometric interpretations to problems of more complexity. The effectiveness of the H diagram is demonstrated by applications that include the selection of prime implicants, expansion about arbitrary subfunctions, and transformation of variable sequences.

M. Karnaugh. The map method for synthesis of combinational logic circuits. Transactions of the American Institute of Electrical Engineers, vol. 72 part I (1953), pp. 593–598.

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The map method for synthesis of combinational logic circuits

THE SEARCH for simple abstract techniques to be applied to the design of switching systems is still, despite some recent advances, in its early stages. The problem in this area which has been attacked most energetically is that of the synthesis of efficient combinational that is, nonsequential, logic circuits.