Synchronous Sequential Logic Research Articles

Chemical reaction network designs for asynchronous logic circuits

Chemical reaction networks (CRNs) are a versatile language for describing the dynamical behaviour of chemical kinetics, capable of modelling a variety of digital and analogue processes. While CRN designs for synchronous sequential logic circuits have been proposed and their implementation in DNA demonstrated, a physical realisation of these devices is difficult because of their reliance on a clock. Asynchronous sequential logic, on the other hand, does not require a clock, and instead relies on handshaking protocols to ensure the temporal ordering of different phases of the computation. This paper provides novel CRN designs for the construction of asynchronous logic, arithmetic and control flow elements based on a bi-molecular reaction motif with catalytic reactions and uniform reaction rates. We model and validate the designs for the deterministic and stochastic semantics using Microsoft’s GEC tool and the probabilistic model checker PRISM, demonstrating their ability to emulate the function of asynchronous components under low molecular count.

A Sequential Logic iLab Utilizing NI ELVIS II+ and the Interactive iLab Architecture

Recent trends in development and utilization of online laboratories have resulted into standard platforms that are not lab-specific, which can be leveraged to develop laboratories in diverse fields. One such platform is the Massachusetts Institute of Technology (MIT) interactive iLab Shared Architecture. This paper presents work undertaken at Makerere University to develop a synchronous sequential logic iLab based on this architecture. The research was carried out by a Graduate researcher, under joint supervision in the confines of the iLab Africa Graduate Fellowship Programme. The research builds on previous work undertaken by the same researcher, in which a combinational digital logic iLab was developed. The sequential logic iLab utilizes the National Instruments Educational Laboratory Virtual Instrumentation Suite (NI ELVIS II+) hardware, with its interactive user interface developed using the Laboratory Virtual Instrument Engineering Workbench (LabVIEW). The generic platform supports experiments in the fields of counters, shift registers, frequency dividers and digital clocks, with appropriate electronic component selection and configuration. The design methodologies and implementation strategies for each experiment category are presented as well as the respective test runs. The laboratory has been used to support courses in the curricula of the Bachelor of Science (B.Sc) in Computer, Electrical and Telecommunication Engineering Programmes at Makerere University.

Improvement of Optimization in Design of Synchronous Sequential Circuits by Using Evolvable Hardware

Evolvable hardware is a new method for designing the digital logic circuits. In this paper, a method has been presented for designing the synchronous sequential logic circuit by using the evolvable hardware. In this approach, the sequential logic circuit is divided into two sections; the combinational logic circuit and DFFs. The combinational logic part is designed by using a constant structure and their connections are set with genetic algorithm (GA). The results show that our method can reduce the average number of generations by limitation the search space.

A Study on Counter Design using Sequential Systems based on Synchronous Techniques

This paper presents a method of design the counter using sequential system based on synchronous techniques. For the design the counter, first of all, we derive switching algebras and their operations. Also, we obtain the next-state functions, flip-flop excitations and their input functions from the flip-flop. Then, we propose the algorithm which is a method of implementation of the synchronous sequential digital logic circuits. Finally, we apply proposed the sequential logic based on synchronous techniques to counter.

Introduction to Logic Synthesis using Verilog HDL

Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system netlists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and progress to synchronous sequential logic systems. Common pitfalls in the development of synthesizable Verilog HDL are also discussed along with methods for avoiding them. The target audience is anyone with a basic understanding of digital logic principles who wishes to learn how to model digital systems in the Verilog HDL in a manner that also allows for automatic synthesis. A wide range of readers, from hobbyists and undergraduate students to seasoned professionals, will find this a compelling and approachable work. The book provides concise coverage of the material and includes many examples, enabling readers to quickly generate high-quality synthesizable Verilog models.

Evolutionary Algorithms and Theirs Use in the Design of Sequential Logic Circuits

In this paper an approach based on an evolutionary algorithm to design synchronous sequential logic circuits with minimum number of logic gates is suggested. The proposed method consists of four main stages. The first stage is concerned with the use of genetic algorithms (GA) for the state assignment problem to compute optimal binary codes for each symbolic state and construct the state transition table of finite state machine (FSM). The second stage defines the subcircuits required to achieve the desired functionality. The third stage evaluates the subcircuits using extrinsic Evolvable Hardware (EHW). During the fourth stage, the final circuit is assembled. The obtained results compare favourably against those produced by manual methods and other methods based on heuristic techniques.

Model partitioning and the performance of distributed timewarp simulation of logic circuits

Simulation of complex digital electronic systems requires powerful machines and algorithms. Distributed simulation could improve both the execution time and the availability of a large distributed memory for complex models. Model partitioning onto the available processors has a major impact on simulation efficiency. We report on how various partitioning algorithms affect timewarp-based distributed simulation of combinational and synchronous sequential logic circuits, and try to determine the relationship between circuit parameters (the number of gates, topological levels and the degree of activity in the circuit) and the structure of the partition having the fastest simulation on a heterogeneous network of Sun workstations.

Logic Simulator:Sequential Logic Minimization

Computer Aided Design (CAD) is a tool that comprises of a program written in Turbo Pascal ver 5.0. This CAD tool is use to minimize the states of synchronous sequential logic automatically. In completely specified case, it will give a minimum solution but in the incomplete case, it does not guarantee to produce a minimum solution. Keywords: state-table, compatible tree, maximal compatible(MC), closure function.

Hierarchical topological sorting of apparent loops via partitioning

Topological sorting (rank ordering) is a highly useful technique for ordering a set of objects according to a precedence relation, producing an ordered list suitable for processing. Applications for topological sorting include compiled logic simulation and timing analysis. While topological sorting is easily accomplished for flat combinational logic networks, hierarchical logic can be difficult to order because feedback may appear in the hierarchical representation even though it is not present in an equivalent flattened representation. This paper presents a new general solution to this problem and describes an efficient algorithm for topological sorting even in the presence of such apparent loops. Its application to hierarchical functional simulation of combinational and synchronous sequential logic is also discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

SSCSSC: a tool for the teaching of digital circuits

The authors present a computer program to support the teaching of digital circuits. The program is used to describe, synthesize, and simulate combinational and synchronous sequential logic circuits, and to help students in their first contact with automatic synthesis tools. The program runs on both MS-DOS and UNIX machines, and it can be given freely to students for home use to significantly reduce the crowding in laboratories. Care has been taken to provide a friendly interface, so that the user can immediately concentrate on the study of circuits instead of having to learn a new program. The software described by the authors is currently used as a support tool in the course on Digital Circuits for Electronic Engineers at the University of Pisa.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Integrated Magnetic Circuits for Synchronous Sequential Logic Machines

The magnetic switching core is a small, reliable and inexpensive component for digital logic circuits, but conventional core circuits also include a large number of auxiliary semiconductor components. As a result, the cost and reliability of core circuits are not very different from those built entirely with semiconductors. The possibility of building logical systems that use a minimum of nonmagnetic components is examined. Except for the provision of clock-pulse sources, fully integrated magnetic machines are feasible in principle. Suitable circuits must contain provision for gain, memory and unilateral transmission of data. These requirements can be met by taking advantage of the threshold characteristics of ferromagnetic materials that have a rectangular hysteresis loop. Two approaches are selected for consideration. In the first, a binary digit is represented by the remanent state of magnetization of a ferrite core. Upon the application of clack pulses its state can be transferred to adjacent cores by means of electrical interconnections. In the second approach, a binary digit is represented by a discrete flux pattern in a continuous flux conductor. These patterns can be propagated in a step-by-step process through the flux conductor by means of clock pulses. Examples are given of experimental synchronous sequential circuits using commercially available multiapertured cores. The capabilities, limitations and organization of these circuits arc discussed.