Synchronous Residual Time Stamp Research Articles

Experimental Evaluation of the Jitter Generated in Timing Transfer

Modern telecommunications networks maintain synchronization and distribute accurate timing information using approaches with strict requirements on clock quality and jitter and wander at interfaces. In the future, packet networks may be used for timing distribution and synchronization e.g. using IEEE 1588v2 specifying the Precision Time Protocol (PTP). Without amelioration, there may be effects on data buffers within telecommunications networks which have been designed with particular assumptions of clock quality. Applications such as digital audio and video also have synchronization requirements and limits on jitter and wander tolerance. Attention is needed on the impact of clock quality due to clock synchronization on the synchronization and jitter and wander limits for data services over networks. A well-understood approach to the transfer of timing for a data service over a packet network is the Synchronous Residual Time Stamp (SRTS) method. We previously presented a novel approach to modelling and visualising jitter spectra in SRTS timing transfer due to jitter in the reference clocks. In this paper, we present experimental results, which validate the appropriateness of our approximations. Experimental results also show the existence of some spectral components not predicted from the modelling. In the paper we discuss the origins of these spectral components.

Quantisation jitter reduction with parameter modulation in SRTS

The parameter modulation method is considered for quantisation jitter reduction in synchronous residual time stamp, and the calculated quantisation jitter reduction effect is verified by experiment.

Non-Compressed Video Signal Optical Transmission Equipment and Its Applications for Studio to Transmitter Link (STL)

This paper describes the newly developed video signal transmission equipment for Synchronous Optical Network (SONET) and the Synchronous Residual Time Stamp (SRTS) method for video signals. It explains why a low jitter signal transmission is possible by optimizing the SRTS parameters and reducing high frequency jitters by PLL circuit. Moreover, the broadcasting Transport Stream (TS) signal transmission methods for Studio to Transmitter Link (STL) are reviewed and the proposed reference clock transmission method is discussed. The TS signal transmission experiments are carried out using two route trunks between Sapporo and Asahikawa, for evaluating the characteristics of the reference clock, the modulator output signal, and the quality of the received video. The low jitter and error-free video signals transmission is realized in these trunks

A new reconstruction approach in the srts method

The synchronous residual time stamp (SRTS) is widely implemented for the transport of the service clock associated with continuous bit-rate services in asynchronous transfer mode adaptation layer 1. We present a new approach to service clock regeneration, which is simple to implement and can be proven to be correct.

Design of ATM circuit emulation service terminal adapter

The asynchronous transfer mode (ATM) Circuit Emulation Service (CES) terminal adapter (TA) is designed for transporting the DS1/E1 tributary in an ATM network. The DS1/E1 tributary are segmented and reassembled by an ATM adaptation layer 1 (AAL1) segmentation and re-assembly (SAR) field programmable gate array (FPGA) in the low-speed circuit board. Synchronous residual time stamp (SRTS) is used to recover the source clock at the receive end. The high-speed board provides a physical layer and ATM layer functions. A cell multiplexer/demultiplexer FPGA, is designed to route cells to each service low-speed boards. The prototype CES-TA is connected to ATM switches and tested for its performance.

Comments on "Determining parameters to minimize jitter generation in the SRTS method"

As discussed by Walker and Cantoni (see ibid., vol.46, no.1, p.82-90, 1998), B-ISDN continuous bit-rate services using the synchronous residual time stamp method may be suspected to suffer from excessive jitter. However, this is not true even if a high-frequency offset shifts the stuff ratio to an unfavorable stuff ratio causing high-jitter amplitude. But there is another, still open, synchronization issue.

Modeling of the synchronization process jitter spectrum with input jitter

The synchronous residual time stamp (SRTS) is one approach approved for the encoding and transporting of the continuous bit rate (CBR) service clock in ATM Adaptation Layer 1 (AAL1) allowing CBR services to be transported in ATM cells over the B ISDN. It has been shown by the authors and others that the SRTS method generates waiting time jitter analogous to that produced by other synchronization processes such as pulse stuffing synchronization. Modeling of the synchronization process as it applies to the SRTS method requires a time domain approach to produce an exact expression of the jitter. In this paper, we apply a new time domain analysis technique previously developed by the authors to derive the expressions for the jitter spectrum of the synchronization process in the presence of input jitter on the service clock. Furthermore, the particular form taken by the jitter spectrum when the input jitter is sinusoidal is also found. Experiments verifying the synchronization process jitter spectrum, both with and without sinusoidal input jitter, are reported. Confirmation is also provided that it is possible to approximate timing jitter by phase jitter as long as certain frequency-amplitude limits are observed.

Waveform analysis of jitter in SRTS using continued fraction

This paper presents a method to analyze jitter waveform in synchronous residual time stamp (SRTS) using continued fraction. It is shown first that the jitter waveform can be decomposed into triangular wave components and that each component corresponds to a rational approximation value of a parameter called residue. Next, quasi-simple continued fraction expansion of the residue is defined to obtain rational approximation values of the residue in a systematic manner. This method gives a series of rational approximation values of the residue. It corresponds to the decomposition of the SRTS jitter waveform into triangular wave components. Many characteristics of the jitter waveform are derived by the quasi-simple continued fraction expansion of the residue. Especially, the average amplitude and period of each triangular wave component are given.

Determining parameters to minimize jitter generation in the SRTS method

The synchronous residual time stamp (SRTS) method has been recommended by the ITU-T as one approach to the transfer of timing information for continuous bit rate (CBR) services being carried by the asynchronous transfer mode (ATM) adaptation layer 1 (AAL1) of the broadband integrated services digital network (B-ISDN). We give an overview of the SRTS method including a description of service clock recovery at the destination. On the basis of analytical expressions derived, we show that even in an ideal SRTS system, where all clocks are jitter-free, the SRTS method inherently generates jitter. We also show that this jitter is equivalent to the so-called waiting time jitter that is found in conventional timing justification techniques. In other systems where waiting time jitter is generated, parameters are chosen in order to minimize the amount of waiting time jitter produced and in which part of the spectrum it is located. We show that for the SRTS method, the choice of parameters to minimize waiting time jitter is quite restricted. For higher service clock frequencies and clocks with large tolerances, it may be impossible to choose parameters to influence the characteristics of the waiting time jitter produced.

Design of ATM AAL1 SAR for circuit emulation

The asynchronous transfer mode (ATM) adaptation layer type 1 (AAL1) segmentation and reassembly (SAR) are designed and implemented by the field programmable gate array (FPGA). The SAR header is generated and processed in the FPGA and the SAR payload is stored in an external first-in-first-out (FIFO) device. A method to recover the source clock, called synchronous residual time stamp (SRTS), is implemented. The designed AAL1 SAR FPGA is properly tested in a prototype circuit board.

Analysis of jitter generated in SRTS method

The characteristics of the jitter generated in the synchronous residual time stamp method used in ATM adaptation layer type 1 is analysed. An exact expression for the jitter waveform is obtained using a time domain method, and the power spectrum of the jitter is derived by a straightforward method.

Jitter in synchronous residual time stamp

This paper presents jitter characteristics of synchronous residual time stamp (SRTS) used in ATM adaptation layer (AAL) type 1. It is pointed out that low frequency jitter appears at the receiver output of SRTS, similar to pulse stuffing synchronization. The jitter waveform in the SRTS is presented together with its Fourier series representation, and the low frequency jitter amplitude is determined. There is a parameter called the residue that plays the same role as the stuffing ratio in pulse stuffing synchronization, where the low frequency jitter amplitude exhibits a peak when the residue is a rational number. It is shown that the jitter waveform and the low frequency jitter amplitude are somewhat different from those obtained by the analog with pulse stuffing synchronization. The dependencies of the low frequency jitter amplitude to some parameters are also considered. It appears that the higher the reference frequency, the smaller the resulting low frequency jitter amplitude. Some numerical examples are given to demonstrate the validity of the analysis.

Distributed source-destination synchronization using inband clock distribution

This paper presents a new distributed methodology for source destination synchronization for interactive teleconferencing. The method is based on a reference clock, which is synthesized from a distributed global clock. The global clock is generated by periodically exchanging inband synchronization signals with neighboring nodes. The timing jitter achieved with this method can be arbitrarily close to the jitter obtained by the centralized synchronous methods which usually use an out-of-band, hard-wired reference clock. The global clock synchronization algorithm, used in this work, guarantees frequency locking of all the network nodes to the slowest clock in the system. As a result, the slowest clock can be used as an implicit reference clock for source-destination synchronization protocols, such as synchronous frequency encoding technique (SFET) and synchronous residual time stamp (SRTS). This inband synchronization method does not require the explicit knowledge of which clock is actually the slowest in the system. Therefore, if the slowest clock fails, then another clock on a different node will be the slowest, and the nodes will use it as a reference clock for the source-destination synchronization protocol. The existing out-of-band reference clock techniques do not have this strong fault tolerant property.

CLAD implementation and experimental results in ATM networks

AbstractIn ATM networks, CLAD functions convert the information source signal to cells and disassemble the ATM cells to yield the original signal. This paper implements a CLAD utilizing synchronous residual time stamp (SRTS) from the one in the method based upon AAL type 1. That transmits signals whose timing is independent of that of the network. It is clarified that the SRTS method generates low‐frequency jitter of the same order as the stuff multiplexing method. the SRTS jitter of the prototype CLAD is measured. A high‐quality NTSC motion picture is transmitted as DS3 (44.736 Mbits/s) coded signals. Furthermore, communication between two FDDI LANs is tested using DS3 data routers. These tests confirm that the CLAD works well.

Three-level traffic shaper and its application to source clock frequency recovery for VBR video services in ATM networks

Studies the traffic shaping issues for VBR video services in ATM networks with stress put on the source clock frequency recovery aspect. The authors propose a three-level traffic shaper (TLTS) which is able to limit the minimum as well as the maximum cell rate of input VBR traffic. For a VBR video source modeled after a two-state Markov modulated Poisson process, they determine, as performance measures, the cell loss probability, the underflow probability, and the maximum delay that a cell can experience in the proposed TLTS. Then they apply the TLTS for source clock frequency recovery in VBR video services. In extending the existing CBR-based synchronous residual time stamp (SRTS) method for VBR video services, it is necessary to restrict the minimum, as well as the maximum, number of cells generated in a fixed period of time to ensure the transmission of timing information, and the proposed TLTS is tailored to meet this necessity by adopting an optimal dimensioning procedure based on the genetic algorithm (GA). Finally the authors provide some numerical examples to demonstrate the optimal dimensioning procedure of TLTS and the related performances of statistical multiplexing and source clock frequency recovery. >

Synchronous techniques for timing recovery in BISDN

Timing recovery for an ATM network is inherently different from its circuit-switched counterpart. There are two generic approaches to ATM timing recovery, namely, non-synchronous methods which rely on cell jitter filtering and synchronous methods which use a common reference clock. The latter approach has better jitter/wander performance. This is particularly significant for circuit emulation of existing hierarchical signals (e.g. DSn signals), which have stringent jitter/wander requirements. This paper compares several methods for timing recovery in a synchronous network environment and discusses the fundamental concept, implementation, and performance of three synchronous techniques: synchronous frequency encoding technique (SFET), time stamp (TS), and synchronous residual time stamp (SRTS). Among these methods, it is concluded that the SRTS method, invented by the authors, is the most efficient. SRTS has been accepted by ITU-T as the timing recovery standard for AAL-1 (ATM Adaptation Layer-Circuit Emulation). Practical implementation considerations of the SRTS technique and its robustness against cell loss are also examined in this paper. In addition, it is shown that a strong analogy can be drawn between SRTS and conventional pulse stuffing synchronization techniques so that the jitter performance for SRTS is comparable to that of the circuit-switched network. >