Synchronous Mirror Delay Research Articles

A Wide-Range All-Digital Delay-Locked Loop for DDR1–DDR5 Applications

A high-speed wide-range all-digital delay-locked loop (ADDLL) suitable for double data rate (DDR1)–DDR5 applications is proposed. The proposed architecture combines the advantages of synchronous mirror delay and delay-locked loop (DLL), which can solve the dynamic tracking problem without requiring a long locking time. In addition, the operating range of the aforementioned architecture is extended through harmonic locking detection and autocalibration technologies. For verification, an experimental chip was fabricated using a 90-nm standard CMOS process with a 1-V power supply. The core area occupies 381 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text {m} \times 234\,\,\mu \text{m}$ </tex-math></inline-formula> . The measurement results indicate that the operating range of the proposed ADDLL was from 0.1 to 2.7 GHz, and the peak-to-peak period jitter was less than 5 ps. The output error was less than 1.9%, and the maximum quadrature phase error was 3.61°.

Wide duty cycle range synchronous mirror delay designs

A wide duty cycle range and small static phase error synchronous mirror delay (SMD) for system-on-chip (SoC) applications is presented. The conventional SMD accepts only the pulsed clock signal and has large static phase error. The proposed SMD uses the edge-trigger mirror delay cell to enlarge the input duty cycle range and the blocking edge-trigger scheme to ensure functionality and performance. Moreover, phase error can be reduced by the proposed delay-matching structure and fine-tuning delay line with a high-resolution delay cell. Simulation results of SMD show that the input clock duty cycle range is from 20 to 80% and the worst static phase error under different process, voltage, and temperature conditions can achieve 18 ps at 400 MHz.

Wide-range synchronous mirror delay with arbitrary input duty cycle

A wide-range synchronous mirror delay (SMD) with arbitrary input duty cycle is presented. The proposed SMD utilises the time-to-digital converter for a frequency-range selector and a multiband delay monitor circuit to achieve a wide range of operating frequencies. The simulation results show that the operating frequency is from 200 MHz to 1 GHz and the static phase error is 6.7 ps. The locking time is less than eight clock cycles: two cycles with coarse tune and six cycles with fine tune.

A high-resolution synchronous mirror delay using successive approximation register

A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the internal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the conventional SMD . Fine locking is achieved by the successive approximation register for the sake of fast locking . Measured results show that the maximum clock skew of the proposed SMD is 140 ps in the frequency range from 170 to 230 MHz and that the consumption power is 14.85 mW at 230 MHz in a 0.35-/spl mu/m 1-poly 4-metal CMOS technology. The total locking time is 10 clock cycles.

A Mixed-Mode Synchronous Mirror Delay Insensitive to Supply and Load Variations

A digital synchronous mirror delay combined with an analog delay-locked loop (DLL) is introduced. Under the influence of process, voltage, temperature, and load variations, the conventional digital synchronous mirror delay could not compensate the static phase error because of its digital type and open loop by nature. The proposed circuit can compensate the delay mismatch between the output buffer and the inner stage, which is caused by the different loading conditions. It can improve the noise immunity from supply variations. Moreover, because of the tracking property of the DLL, the static phase error and jitter could also be reduced. The proposed circuit has been fabricated by a CMOS 0.35-μm one-poly four-metal process and the whole chip area is 1.47 × 1.07 mm2 including I/O pad peripherals. The measured peak-to-peak jitter is 16.4 ps at supply voltage of 3.3 V and frequency of 300 MHz. The power consumption of the entire chip is 16.5 mW for analog part and 84 mW for digital part. The comparisons between the proposed circuit and the conventional digital synchronous mirror delay are also demonstrated.

Synchronous Mirror Delay for Multiphase Locking

A clock generation circuit having the function of multiphase locking was designed using the synchronous mirror delay (SMD) scheme. The internal clock can be synchronized to the external clock with intended phase difference. The synchronizing error of the clock generation circuit is reduced below the delay time of unit delay stage by compensation characteristics of detecting circuit in SMD. A 32-M double data rate (DDR) SRAM including the clock generation circuit is fabricated using 0.13-/spl mu/m CMOS technology. To measure the synchronizing error of the clock generation circuit, the test elements group (TEG) system is designed and fabricated with the main system. The synchronizing error of the clock generation circuit is far smaller than the delay time of unit delay stage at zero phase locking and similar to the delay time of unit delay stage at multiphase locking.

Low power clock generator based on area-reduced interleaved synchronous mirror delay

A new interleaved synchronous mirror delay (SMD) is proposed to reduce circuit size. In addition, the proposed interleaved SMD solves the polarity problem with just one extra inverter. Simulation results show that about 30% power reduction and 40% area reduction are achieved in the proposed interleaved SMD.

An analog synchronous mirror delay for high-speed DRAM application

An analog synchronous mirror delay (ASMD) is proposed, which provides fast locking characteristics in recovery from power-down mode in a DRAM application. As an open-loop fast locking system, ASMD measures and compensates the skew between external and internal clocks in analog operation mode within two cycles of an input clock using a charge-pumping scheme. This ASMD has no static phase error problem, which is related to the path selection operation of previously implemented SMD schemes. To enhance the linearity of delay characteristics and to increase the maximum operating frequency, dual pumping and multiple folding schemes are also proposed. An experimental chip with basic ASMD configuration is fabricated using 0.6-/spl mu/m double-metal CMOS technology to verify the feasibility of the proposed scheme. With functional blocks of the charge pump, comparator, and control pulse generator, it occupies an area of 1.1/spl times/0.7 mm/sup 2/. An experimental ASMD has a working range of 100-300 MHz at 3.3 V with peak-to-peak jitter of 140 ps/spl plusmn/200 mV of sinusoidal supply noise of 1 MHz added, and power dissipation of 30 mW at 250-MHz clock input.

A direct-skew-detect synchronous mirror delay for application-specific integrated circuits

A nonfeedback CMOS digital-clock-generator, direct-skew-detect synchronous-mirror-delay (direct SMD) circuit has been developed that achieves clock-skew suppression in only two clock cycles for application-specific integrated circuits having unfixed and various clock paths. The direct SMD circuit detects both clock skew and clock cycle by using a direct-skew detector and clock-suspension circuitry. The skew-detection scheme removes the phase errors caused by delay in the clock-driver circuit. Measurements demonstrated that the direct SMD circuit eliminates various amounts of clock skew (2.0-3.0 ns) at 200 MHz in two clock cycles.

A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay

A 256-Mb SDRAM (245.7 mm/sup 2/) has been developed using (1) a high cell occupation ratio (60.2%) array design for chip size reduction and a high yield, (2) a prefetched pipeline scheme (PPS) using a first-in first-out (FIFO) buffer with parallel serial converter for 250-MHz clock frequency operation, and (3) a synchronous mirror delay (SMD) circuit for 2.5-ns clock access and low standby current.