An analog synchronous mirror delay for high-speed DRAM application

Abstract

An analog synchronous mirror delay (ASMD) is proposed, which provides fast locking characteristics in recovery from power-down mode in a DRAM application. As an open-loop fast locking system, ASMD measures and compensates the skew between external and internal clocks in analog operation mode within two cycles of an input clock using a charge-pumping scheme. This ASMD has no static phase error problem, which is related to the path selection operation of previously implemented SMD schemes. To enhance the linearity of delay characteristics and to increase the maximum operating frequency, dual pumping and multiple folding schemes are also proposed. An experimental chip with basic ASMD configuration is fabricated using 0.6-/spl mu/m double-metal CMOS technology to verify the feasibility of the proposed scheme. With functional blocks of the charge pump, comparator, and control pulse generator, it occupies an area of 1.1/spl times/0.7 mm/sup 2/. An experimental ASMD has a working range of 100-300 MHz at 3.3 V with peak-to-peak jitter of 140 ps/spl plusmn/200 mV of sinusoidal supply noise of 1 MHz added, and power dissipation of 30 mW at 250-MHz clock input.