Synchronous Circuits Research Articles

Design Of Modified Data Driven Clock Gating And Look Ahead Clock Gating For Low Power

Clock signal is considered as an immense source of power dissipation in synchronous circuits because of large frequency and load. It does not carry any information but consumes high power at the switching activity which is to be avoided. So, by using clock gating we can save power by reducing unnecessary transition activity inside the gated module. Hence modified design of data driven clock gating and look ahead clock gating is designed to obtain the less power in the circuits. These two techniques are compared among them and by the results obtained through cadence virtuoso tool we can conclude that look ahead clock gating consumes low power, low noise response and higher performance.

A Comprehensive Analysis and Modeling of the Self-Powered Synchronous Switching Harvesting Circuit With Electronic Breakers

Self-powered realization for synchronous switching circuits is a hot spot for piezoelectric vibration energy harvesting. As a well-known approach, the electronic breaker is widely used for its simplicity and reliability. It plays an important role on the performance of the piezoelectric generator by affecting the available open-circuit voltage and the switching phase lag. In this paper, a comprehensive model is developed for improved performance analysis with missed factors included in comparison with previous investigations. The combined influence of the envelope resistor and the capacitor on both the phase lag and the open-circuit voltage is newly considered while the additional phase lag effect induced by charging the switch parasitic capacitance with the envelope capacitance is supplemented. Experiments and simulations validate the proposed model with better accuracy and the results show that these supplemented factors are important to the generator performance, especially for the micropower energy harvesting with small piezoelectric capacitance or displacement magnitude. Moreover, more detailed design guidelines are deduced from the proposed model.

Compact self-powered synchronous energy extraction circuit design with enhanced performance

Synchronous switching circuit is viewed as an effective solution of enhancing the generator’s performance and providing better adaptability for load variations. A critical issue for these synchronous switching circuits is the self-powered realization. In contrast with other methods, the electronic breaker possesses the advantage of simplicity and reliability. However, beside the energy consumption of the electronic breakers, the parasitic capacitance decreases the available piezoelectric voltage. In this technical note, a new compact design of the self-powered switching circuit using electronic breaker is proposed. The envelope diodes are excluded and only a single envelope capacitor is used. The parasitic capacitance is reduced to half with boosted performance while the components are reduced with cost saved.

Modeling and Energy Optimization of LDPC Decoder Circuits With Timing Violations

This paper proposes a “quasi-synchronous” design approach for signal processing circuits, in which timing violations are permitted, but without the need for a hardware compensation mechanism. The case of a low-density parity-check (LDPC) decoder is studied, and a method for accurately modeling the effect of timing violations at a high level of abstraction is presented. The error-correction performance of code ensembles is then evaluated using density evolution, while taking into account the effect of timing faults. Following this, several quasi-synchronous LDPC decoder circuits based on the offset min-sum algorithm are optimized, providing a 23%–40% reduction in energy consumption or energy-delay product, while achieving the same performance and occupying the same area as conventional synchronous circuits.

Measurement of a 3D Ultrasonic Wavefield Using Pulsed Laser Holographic Microscopy for Ultrasonic Nondestructive Evaluation.

In ultrasonic array imaging, 3D ultrasonic wavefields are normally recorded by an ultrasonic piezo array transducer. Its performance is limited by the configuration and size of the array transducer. In this paper, a method based on digital holographic interferometry is proposed to record the 3D ultrasonic wavefields instead of the array transducer, and the measurement system consisting of a pulsed laser, ultrasonic excitation, and synchronization and control circuit is designed. A consecutive sequence of holograms of ultrasonic wavefields are recorded by the system. The interferograms are calculated from the recorded holograms at different time sequence. The amplitudes and phases of the transient ultrasonic wavefields are recovered from the interferograms by phase unwrapping. The consecutive sequence of transient ultrasonic wavefields are stacked together to generate 3D ultrasonic wavefields. Simulation and experiments are carried out to verify the proposed technique, and preliminary results are presented.

An Efficient Self-Powered Piezoelectric Energy Harvesting CMOS Interface Circuit Based on Synchronous Charge Extraction Technique

An efficient self-powered synchronous electric charge extraction CMOS interface circuit dedicated to piezoelectric harvesters is proposed in this paper. Self-powered peak detection (PKD) and switch circuits are used to reduce quiescent current so that the backup or pre-charged power can be saved. A new low phase lag (LPL) PKD circuit is designed to improve the synchronous extraction efficiency, which only requires one detection capacitor to perform positive and negative PKD. The circuit can be set at general mode (G-mode) or LPL mode (LPL-mode). Under LPL-mode, the phase lag can be reduced typically by 50%, the synchronous extraction efficiency can obtained up to 94%, while the output power can reach 659 μW when the piezoelectric transducer original opencircuit voltage Voc,org = 5 V, which is 3.56 times of that of full-bridge rectifier standard energy harvesting circuit at the maximum power point. The minimum harvesting startup voltage is 1.7 V and is independent of the energy storage capacitor voltage VDC. The harvesting efficiency can still reach 71.3% at Voc,org = 5 V. The size of the active area is 0.5 mm2 in a 0.18-μm CMOS technology. Circuit may be invoked as a functional block for energy autonomous wireless sensor network node of the Internet of Things.

The design of synchronization circuit for crossing the clock domain in multi clock system

The design of synchronization circuit for crossing the clock domain in multi clock system

Exact Timing Analysis for Asynchronous Systems

Analyzing the timing properties of asynchronous systems is essential for characterizing their performance and power. Previous work on timing showed that such systems under and-causality and fixed delay exhibit periodicity properties. We give a different graph-based rigorous proof of the exact timing behavior of more general classes of such systems, and conclude their exact periodicity property, where each of the signal transition will occur with the same period after finite occurrences. We established our results under weaker assumption about system connectivity/topology, and this paper provides the theoretical foundation, for the exact periodicity property to be applied and exploited in circuits containing a combination of synchronous and asynchronous components. We provide simulation-based results for several typical asynchronous circuit topologies to quantify this time period in practical circuits. We also provide an extension of our analysis and methods to the case of bounded delay systems. A key result that is a consequence of our analysis is that asynchronous circuits can be integrated with synchronous logic via a metastability-free interface, thereby eliminating the high-overhead synchronizers when an asynchronous circuit is fully surrounded by synchronous logic.

DAMSEL—Dynamic and Applicative Measurement of Single Events in Logic

This paper describes a circuit called dynamic and applicative measurement of single events in logic (DAMSEL), which can individually measure the impact of single event upsets and single-event transients (SETs) in realistic, synchronous digital circuits. Heavy-ion and pulsed laser test results are presented. Both a simple digital and an analog simulation methodology are demonstrated to provide similar cross sections to those observed during the tests. Overall, the DAMSEL structure has many advantages over current circuits used for measuring SETs, including the ease with which test results can be extrapolated to real designs.

Low-Cost Pseudoasynchronous Circuit Design Style With Reduced Exploitable Side Information

Leakage of information through the power supply current has become a major factor in logic design. In this paper, a low cost and simple to employ design methodology dubbed pseudoasynchronous is presented. This design style combines the security advantages of asynchronous circuits with the ease of synchronous circuit design. Randomization and data-dependencies (DD) are utilized to hide information leakage from the current dissipation, and hence making the critical synchronization of power supply current traces hard to do. In addition, randomization and DD are utilized for both time-domain hiding of information leakage during the active region (dynamic currents) and for amplitude-domain hiding of information leakage during the static-region (leakage currents). The main advantages of this new approach are low area cost, reduced signal, and increased noise. Circuit-level analyses show that it is harder to exploit the information leakage from internal signals of the proposed design than from CMOS-based synchronous designs or other forms of time-domain hiding countermeasures.

A Simple Synchronization Logic Aided Interleaved Fly-Back MIC for Grid Interactive Photovoltaic Power System

In this paper, an interleaved fly-back converter based module integrated converter (IFBC-MIC) for grid interaction of photovoltaic (PV) system is presented. MIC grid integration technology received wide acceptance in PV applications and may assist in achieving maximum power generation for mismatched or partially shaded PV modules by independent control of individual PV modules according to their insolation levels, giving substantially higher output power.This paper develops a MIC system involving interleaved fly-back converter to minimize the switching ripple of the dc link voltage and a simple zero crossing detectors (ZCD) circuits based gird synchronization circuit to avoid the complex phase locked loop (PLL). The proposed system includes the Perturb and Observe (P&O)Maximum Power Point Tracking(MPPT) to enhance the PV power extraction.A 100W PV system is considered for the MATLAB based simulation study and hardware experimentation. Simulation and hardware results prove that the suggested system is highly suitable for portable PV applications.

Chemical reaction network designs for asynchronous logic circuits

Chemical reaction networks (CRNs) are a versatile language for describing the dynamical behaviour of chemical kinetics, capable of modelling a variety of digital and analogue processes. While CRN designs for synchronous sequential logic circuits have been proposed and their implementation in DNA demonstrated, a physical realisation of these devices is difficult because of their reliance on a clock. Asynchronous sequential logic, on the other hand, does not require a clock, and instead relies on handshaking protocols to ensure the temporal ordering of different phases of the computation. This paper provides novel CRN designs for the construction of asynchronous logic, arithmetic and control flow elements based on a bi-molecular reaction motif with catalytic reactions and uniform reaction rates. We model and validate the designs for the deterministic and stochastic semantics using Microsoft’s GEC tool and the probabilistic model checker PRISM, demonstrating their ability to emulate the function of asynchronous components under low molecular count.

Two Approaches for Timing-Driven Placement by Lagrangian Relaxation

In this paper, we propose Lagrangian relaxation (LR)-based algorithms to optimize both circuit performance and total wirelength at the global placement stage. We introduce a general timing-driven global placement problem formulation that is applicable to three different circuit design styles: 1) synchronous circuits; 2) synchronous circuits with sequential optimization techniques; and 3) asynchronous circuits. LR is applied to handle the timing constraints of the formulated problem. Based on how the cell spreading constraints are handled, two different approaches are proposed: one approach handles the spreading constraints inside the LR framework and transforms the timing-driven placement (TDP) problem into a series of weighted wirelength minimization problems, which can be solved by directly leveraging existing wirelength-driven placers. The other approach handles the spreading constraints outside the LR framework. Thus, only timing constraints need to be taken care of in the LR framework and better solutions can be expected. In both approaches, we simplified the LR subproblem using Karush–Kuhn–Tucker conditions. Our algorithms are implemented based on a state-of-the-art wirelength-driven quadratic placer. The experiments demonstrate that the proposed algorithms are able to achieve significant improvements on circuit performance compared with a commercial wirelength-driven placement flow and a commercial asynchronous TDP flow.

DC Polarity Control in Radio Frequency Synchronous Rectifier Circuits

In this letter, two different switching modes are identified for RF synchronous rectifier circuits which lead to a change in the polarity of the rectified output voltage. The operation of the two modes is defined in terms of the dynamic current-voltage (I-V) characteristics of the switching device and the polarity of the output load voltage. In one mode, the dc output voltage is positive and associated with a switching condition where the device is ON in quadrant-III and OFF in quadrant-I. This mode of operation has been reported widely in the literature. In the second mode, the quadrants associated with the on- and off-state are swapped leading to a polarity reversal across the load. Theoretical justification for the two modes is given and the experimental results are shown to confirm the two different switching modes in the synchronous rectifier. Experiments with a GaN inverse class-F rectifier were made to verify the theory, and both modes have similar measured peak rectification efficiencies of 77% at a frequency of 1.8 GHz.

High-performance dynamic elastic pipelines

In this paper, we will propose a new class of synchronous elastic pipelines called Dynamic Elastic Pipeline (DELP) that employs dynamic logic family and achieves improved throughput and elasticity. Since these pipelines are synchronous, they can be supported by Electronic Design Automation (EDA) flows, and as they are elastic, they benefit from elasticity of asynchronous circuits. In synchronous elastic circuits, elasticity is like that they are able to stretch or shrink the clock's pulses with a constant step. PS0 style, as well as conventional synchronous Static ELastic Pipeline (SELP) are used as the reference point, yet achieve remarkable improvements through novel control circuit optimizations. This paper concentrates on designing very fine-grain or gate-level pipelines in which the datapath is partitioned into stages with only a single level depth logic. Two new single-rail and dual-rail pipelines have been implemented and all implementations have been characterized by low-cost control structures and latchless design. Post-layout simulations in 90 nm technology reveal that the proposed dual-rail DELP design has 19.1% higher throughput than that of Williams’ PS0. Also, comparing to the synchronous SELP, our novel single-rail DELP achieves 52.4% higher throughput.

An Aging-Aware Reliable FinFET-Based Low-Power 32-Word $$\times $$ × 32-bit Register File

As the VLSI technology is heading toward deep subnanometer range, the NBTI effect has emerged as a major reliability issue for the state-of-the-art CMOS as well as FinFET-based circuits. NBTI causes an incremental deviation in the threshold voltage of PMOS and hence causes variation in timing of digital circuits. Further, NBTI may increase the delay of circuits which are lying in the critical path of a system. This timing mismatch is a serious concern for synchronous clock-based circuits such as dynamic logic gates employed in a register file which itself lies in the critical path of a microprocessor. This is a critical reliability issue for microprocessors and microcontrollers which are used in electronic systems with high lifetime such as sensors. This paper has introduced a reliable FinFET-based low-power 32-word \(\times \) 32-bit register file which is designed using 32-nm BSIM-IMG technology. In this paper, the impact of NBTI on the different modules of FinFET-based register file has been studied. This analysis reveals that the domino OR gate bit-line is responsible for much of the NBTI degradation in a register file. Hence, a novel aging-aware domino bit-line has been proposed here which is capable of maintaining a constant performance under NBTI degradation. This proposed domino bit-line is further used to design a novel register file which is capable of maintaining a constant performance for a lifetime of more than 10 years.

Limit‐cycle oscillation reduction in high‐efficiency wireless power receiver

A simple and effective technique is presented to reduce the limit-cycle oscillation (LCO) in the reconfigurable rectifier for wireless power receiver. It is theoretically analysed that only one switching edge of the switching signal is needed to be synchronised and a phase-shift circuit is proposed for synchronisation. Simulation results in commercial 0.18 µm CMOS technology show that the LCO is greatly suppressed with the proposed synchronisation circuit and the output voltage ripples are much smaller compared to the conventional circuit.

Optimization and Design of Integrated Space Target

Background & Objective: The design and optimization of laser detection system based on MEMS (Micro-electro Mechanical Systems) scanning mirror is presented in the paper. According to requirements of application, it adopts the laser module to design the laser driver circuit, and the designed modulation circuit can satisfy the actual needs. Method: The designed information processing module is composed of the echo receiving module, signal amplification and filter circuit module, and the synchronous circuit of measuring angle and distance, etc. Conclusion: It gives out the distance decoding method and explores the method of capturing echo signal, which can fast and accurately calculate the distance and azimuth information of scanning.

Controlled Limiter in the Synchronous Detection Circuit

This variant of construction of the electrical circuit is aimed at reducing the effects of impulse noise. The measuring channels of the primary transducers are subject to interference of various types. In the case of a small ratio between a useful signal and noise level, synchronous detection is used. Impulse noise leaves a big mark even after using synchronous detection. To improve the performance of such measuring devices, it is proposed to use a controlled amplitude limiter at the input. Comparative analysis of solutions with controlled limiters is carried out in the article and conditions for its optimal operation are determined.

Singular Perturbations of Volterra Equations with Periodic Nonlinearities. Stability and Oscillatory Properties

Singularly perturbed integro-differential Volterra equations with MIMO periodic nonlinearities are considered, which describe synchronization circuits (such as phase- and frequency-locked loops) and many other “pendulum-like” systems. Similar to the usual pendulum equation, such systems are typically featured by infinite sequences of equilibria points, and none of which can be globally asymptotically stable. A natural extension of the global asymptotic stability is the gradient-like behavior, that is, convergence of any solution to one of the equilibria. In this paper, we offer an efficient frequency-domain criterion for gradientlike behavior. This criterion is not only applicable to a broad class of infinite-dimensional systems with periodic nonlinearities, but in fact ensures the equilibria set stability under singular perturbation. In particular, the proposed criterion guarantees the absence of periodic solutions that are considered to be undesirable in synchronization systems. In this paper we also discuss a relaxed version of this criterion, which guarantees the absence of “high-frequency” periodic solutions, whose frequencies lie beyond a certain bounded interval.