Synchronous Circuits Research Articles

SPICE Simulation Assisted-Dynamic Rds(on) Characterization in 200V Commercial Schottky p-GaN HEMTs Under Unstable Phases

Abstract This paper presents a comprehensive analysis of dynamic and static RDS(ON) in Schottky p-GaN High Electron Mobility Transistors (HEMTs), highlighting the impact of off-state and hot electron trapping on device performance. The authors observed significant hysteresis in the transfer characteristics of a 200V commercial Schottky p-GaN, attributing this to charge trapping effects. A novel experimental setup, employing a multi-pulse test synchronous buck converter circuit with additional gate control and a clamping circuit, enabled precise characterization of dynamic RDS(ON) under varying conditions, including unstable phases with overcurrent. This method effectively mimics solar PV input scenarios, exposing the device to high dv/dt and di/dt stresses, which are critical for evaluating GaN device stability under transient conditions. This research also reveals that increased gate resistance reduces energy losses, challenging traditional expectations by demonstrating the nuanced gate charge dynamics of GaN HEMTs. This study overall contributes to the understanding of GaN device behavior, offering a novel approach for accurately characterizing dynamic RDS(ON) under unstable stages, furtherly advances the GaN device in complex renewable energy power converter applications.

A Self-Sensing Synchronous Switch Circuit for Bidirectional Piezoelectric Energy Conversion

A Self-Sensing Synchronous Switch Circuit for Bidirectional Piezoelectric Energy Conversion

Development of a large-area array multi-point synchronous explosive circuit using sheet explosive detonated by a mild detonating fuse

Development of a large-area array multi-point synchronous explosive circuit using sheet explosive detonated by a mild detonating fuse

Sensitive and High-Throughput Time-Resolved Luminescence Detection of Tetracycline in Milk for Eliminating Background Fluorescence on a Miniaturized Apparatus.

Fluorescence detection has always suffered from high background fluorescence from real samples such as milk. Therefore, cumbersome pretreatments of samples were necessary to remove the fluorescent substances but led to long processing times and low efficiency. Time-resolved luminescence detection is a powerful technique for eliminating short-lived background fluorescence without additional pretreatments. However, the related instruments are usually equipped with high-speed excitation sources and detectors, which are always bulky and expensive. Herein, we developed a low-cost and miniaturized imaging system for high-throughput time-gated luminescence detection. An UV LED array was used to excite multiple samples, the luminescence of which could be detected by a smartphone simultaneously. An analog circuit was designed to synchronize the LED to the mechanical chopper to eliminate the background signals resulting from scattering and short-lived autofluorescence. Compared to other synchronous circuits based on FPGAs and microcontrollers, this analog circuit required no programming and memory. For the first time, high-throughput time-resolved luminescence detection of tetracycline in milk without any separation or enrichment was achieved by utilizing a smartphone as a camera, and the scattered signals and the background fluorescence were eliminated efficiently. The limit of detection reached as low as 53 nM (∼0.024 ppm), lower than the residue limit set by the European Union. This high-throughput time-gated luminescence detection method can be used for quantitative analysis of many real samples with high background fluorescence.

A Frequency Up-Conversion Piezoelectric Energy Harvester Shunted to a Synchronous Electric Charge Extraction Circuit.

A frequency up-conversion piezoelectric energy harvester (FUC-PEH) consists of a force amplifier, a piezoelectric stack, a low-frequency oscillator (LFO), and a stop limiter. The force amplifier generates the amplification of stress on the piezoelectric stack. The LFO, comprising a spring and a mass block, impacts the stop limiter during vibration to induce high-frequency oscillations within the piezoelectric stack. In this paper, we represent and simplify the FUC-PEH as a lumped-parameter model based on piezoelectric material constitutive equations and structural dynamic theories. Using the electromechanical analogy, we developed an equivalent circuit model (ECM) of the FUC-PEH. A parametric study was performed to investigate the impact of system parameters, such as spring stiffness and concentrated mass, on the FUC-PEH performance. The collision-induced amplitude truncation (AT) effect enlarges the operation bandwidth. ECM simulations show that low-frequency input excitation is converted into a high-frequency output response, enhancing the energy conversion efficiency. Furthermore, we aimed to improve the FUC-PEH's performance using a synchronous electric charge extraction (SECE) circuit. Using the ECM approach, we established a system-level model that considers the electromechanical coupling behavior. The simulation results provide insights into the performance of FUC harvesters with SECE circuits and offer valuable design guidance.

A 16-bit 18-MSPS flash-assisted SAR ADC with hybrid synchronous and asynchronous control logic

This paper presents a 16-bit, 18-MSPS (million samples per second) flash-assisted successive-approximation-register (SAR) analog-to-digital converter (ADC) utilizing hybrid synchronous and asynchronous (HYSAS) timing control logic based on an on-chip delay-locked loop (DLL). The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter (CDAC) than the synchronous and asynchronous SAR ADC. Therefore, the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent. In addition, the foreground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter (FIR-BPF) based least-mean-square (LMS) algorithm in an off-chip FPGA (field programmable gate array). Fabricated in 40-nm CMOS process, the prototype ADC achieves 94.02-dB spurious-free dynamic range (SFDR), and 75.98-dB signal-to-noise-and-distortion ratio (SNDR) for a 2.88-MHz input under 18-MSPS sampling rate.

An efficient self-powered piezoelectric energy extraction scheme with cascaded-gyrators-based transformer

The enhancement of power transfer from the piezoelectric transducer to the load with a compact size is explored in this paper. Large physical inductors are no more required to create resonance in piezoelectric energy harvesting schemes while applying the proposed gyrator-induced double resonance (GI-DR) technique. Hence, the proposed circuit is cost-effective and provide improved performance along with reduced-space benefits in integrated circuits (IC) package for wireless sensor nodes (WSN) and Internet-of-Things (IoT) applications. Two cascaded gyrators are used in place of a transformer in the proposed circuit. The required phasor response for resonance is acquired by the gyrators' voltage-current (V–I) relationship. Regarding the final charging voltage, the proposed circuit with a storage capacitor of 1000 mF can obtain 763.46 % and 14.77 % improved performance than other synchronous circuits like SEH and DSSH respectively. The proposed technique can also be applied to similar piezoelectric energy harvesting strategies with large inductors to create resonance.

Fusion synapse by memristor and capacitor for spiking neuromorphic systems

Research on neuromorphic computing with spiking neural networks and in-memory computing to achieve low-power consumption and high-speed operation has received great attention. In this study, we proposed a new synaptic device called a fusion synapse that consists of a memristor and a capacitor connected in a series and uses a change in the time constant as a synaptic weight. We also prepared both neuron and synchronizer circuits to utilize the time constants as synaptic weights and trained them with PyTorch according to two models. One model is based on previous research, and the other is an aware model of circuit information. We converted the synaptic weights generated by the training into conductance. When assembling two models for inference, 95% accuracy was achieved on MNIST, and the power consumption per inference was 640 nJ. The accuracy was comparable to related research, and considering Dennard scaling, the power consumption was lower than the digital implementation.

Examination and experimental comparison of dc/dc buck converter topologies used in wireless electric vehicle charging applications

The studies on Wireless Power Transfer (WPT) technology and peripherals in Electric Vehicle (EV) applications are intensifying. While the energy received from the WPT system is transferred to the EV battery, the direct current (dc)/dc converter circuits are used. The dc/dc buck converter topologies are one of them. The converter circuits must be highly efficient, lightweight, and compact to have a high range in EV vehicles. There are asynchronous buck, synchronous buck, and interleaved synchronous buck converter circuit topologies from the literature. In this study, the efficiency results of these circuit topologies were analyzed using MATLAB/Simulink and experimental studies. This study contributes to the literature by conducting circuit-level efficiency analysis and component-level power loss analysis. It has been observed that the interleaved synchronous buck converter circuit operates at 99% efficiency at 1066 W. In addition, it has been shared with the oscilloscope results that the current ripples of this circuit topology are lower than other circuit converters. Specifically, there has been a significant reduction of 56% in power losses, particularly in the interleaved synchronous buck converter (ISBC). This study analyzes the dynamic behavior of the dc/dc buck converter topologies, and results about their performance are given.

High-Performance Light Emitting Diode Lighting Circuits and Their Interior Design Applications

This study explores the application of the half-bridge Inductor-Inductor-Capacitor (LLC) resonant converter in Light Emitting Diode (LED) lighting driver power supplies, with a specific focus on improving efficiency and dimming capabilities. The investigation begins with an analysis of the sliding mode control (SMC) method, utilizing a constant-current design with a fixed switching frequency (FWF). A novel fuzzy frequency-selective SMC dimming strategy is proposed to recognize the challenge of significant output voltage ripple during dimming under a FSF. To address the ripple issue during dimming, an electromagnetic filtering circuit is designed, and a zero-voltage turn-on Metal—Oxide—Semiconductor (MOS) tube is introduced, incorporating a synchronous rectification scheme to mitigate losses in the secondary-side rectification diode. The study comprehensively considers a current-mode self-driven method, specifically tailored to the LLC circuit’s different operating modes. The LLC resonant circuit, along with the subsequent synchronous rectification circuit, is meticulously designed for a 252 W LED driver power supply prototype. A closed-loop simulation circuit model is developed using PSIM software in experimental validation. The feasibility of SMC based on a FSF is affirmed through a comparative analysis of SMC signal waveforms, steady-state output current (OC) models, and resonant tank current waveforms. The investigation into the OC under various SMC conditions demonstrates the half-bridge LLC resonant converter’s ability to achieve stable output with minimal ripple. The designed LED lighting circuit is applied to indoor design, providing adjustable LED brightness and switch status at different power levels. Although obstacles slightly impact the communication quality of the circuit, it remains suitable for the majority of users’ needs.

A dynamic voltage scaling circuit design based on critical path replica and time warning techniques

Critical path replica (CPR) is a widely used technique in synchronous digital circuit design. However, the existing CPR technique cannot accurately reflect the timing of the circuit due to local process variations (LPV). An improved CPR technique based on load capacitance matching (LCM) is proposed in this paper, which can track critical path delay across wide voltage range. The impact of LPV is simulated under wide voltage range, and a configurable delay line is designed to eliminate the effect of LPV. Furthermore, a low overhead mixed-threshold transition detector (TD) circuit is also proposed to monitor timing violations of the replica path, which generate an ‘error’ signal used to dynamically regulate the chip’s operating voltage. The proposed techniques are implemented on a CORDIC chip using the 55-nm CMOS process. Simulation results show that in the near-threshold voltage (NTV) region, the supply voltage can be reduced from 0.8 to 0.6 V, enabling a maximum of 42.6% power saving at the TT corner, 25°C with lesser than 1% area overhead as compared to the baseline design.

Permanent magnet synchronous motor inter-turn short circuit diagnosis based on physical-data dual model under oil-drilling environment

Inter-turn Short Circuit (ITSC) faults in Permanent Magnet Synchronous Motor (PMSM) have gained significant attention due to the growing demand for enhanced reliability and safety in actuation systems. This paper presents a adaptive fault diagnosis approach specifically designed for ITSC faults in PMSM used in oil-drilling applications, where sparse actual data and varying speed conditions pose considerable sparse training data and ITSC feature extraction challenges respectively. To address these challenges, we first construct a physical fault model of PMSM-ITSC and establish a simulation experiment platform to replicate downhole environments with high temperatures and rapidly changing PMSM speeds, ensuring a reliable data source for analysis. Subsequently, we propose a novel adaptive peak-to-peak self-finding method (APPS) that leverages frequency-domain prior knowledge to adaptively extract ITSC fault characteristics, even amidst drastic changes in PMSM speed. Furthermore, we introduce the time-sequence efficient moving window self-attention network (EMWSAN) data model for inferring the stator phase winding state, incorporating Half-sandwich and Cascaded windows group attention operations. This approach significantly reduces computational complexity and network parameters compared to traditional self-attention mechanisms. To expedite the fitting process, we apply transfer learning (TL) theory, transferring knowledge from the physical knowledge to the data model, enabling EMWSAN to be trained more efficiently. As a result, our proposed ITSC fault diagnosis scheme achieves an impressive 96.72% classification accuracy, achieving existing state-of-the-art methods.

A Synchronous Current Inversion and Energy Extraction Circuit for Electromagnetic Energy Harvesting Enhancement

A Synchronous Current Inversion and Energy Extraction Circuit for Electromagnetic Energy Harvesting Enhancement

Diagnosis of Oil Drilling Permanent Magnet Synchronous Motor Inter-turn Short Circuit Under Physical Fault Model Training Sample

Diagnosis of Oil Drilling Permanent Magnet Synchronous Motor Inter-turn Short Circuit Under Physical Fault Model Training Sample

Self-sensed, self-adapted and self-powered piezoelectric generator architecture by synchronous circuits of autonomous parameter tuning

Synchronous circuits are effective to enhance the performance of piezoelectric generators and further show the capability of extending the generator’s bandwidth by tuning the switching parameters due to the electromechanical coupling effect. However, many studies are limited to theoretical investigations or restricted experimental conditions with externally powered controllers. Besides, a critical and unsolved challenge for the circuit controller is the sensing of the generator’s dynamics for the tuning of the operation parameters of the synchronous circuits since the switching timing cannot be ensured for varied generator dynamics due to the electromechanical effect of the tunable circuit. This paper presents a new self-powered autonomous piezoelectric energy harvesting system with an integrated structural and electrical design, including a dedicated self-sensed generator and a self-adaptive synchronous interface circuit. The system can automatically tune the extraction parameters (the switching phase and the voltage flip ratio) according to the self-sensed information by utilization of a precise maximum power tracking strategy for optimized power and bandwidth. Compared to the system with the classical synchronous circuit, the proposed design demonstrates superior power harvesting capabilities (0.7125mW@0.05 g), extended bandwidth (2.5 Hz, 471 % of the conventional approach) and excellent adaptability (a tunable and self-sufficient frequency range of 10.6 Hz at 0.1 g acceleration).

A 0.25-μm HV-CMOS Synchronous Inversion and Charge Extraction Interface Circuit With a Single Inductor for Piezoelectric Energy Harvesting

A 0.25-μm HV-CMOS Synchronous Inversion and Charge Extraction Interface Circuit With a Single Inductor for Piezoelectric Energy Harvesting

Design of synchronous frequency dividers in 5‐nm FinFET CMOS technology

AbstractA method is presented for the design of high‐speed frequency dividers in which the divided output signals are phase aligned by means of a scheme based on cascaded retiming. The objective of the design method proposed is to break the accumulation of propagation delay occurring in a divider chain that may limit the speed of the phase synchronization. Compared to alternative approaches where the phase synchronization is achieved with additional logical gates applied to the divider outputs, the authors’ approach only uses latches that are identical to those already employed in the divider chain itself without any additional synchronization logic. Hence, a better uniformity and homogeneity of the layout can be achieved, which helps improve the phase balancing. The method proposed to design synchronous dividers has been implemented in 5‐nm FinFET CMOS technology by means of a synchronous 8b‐counter providing the division factors 1/2 through 1/256. Its output phase synchronization has been verified in measurements at 10 GHz. The measured power consumption is 720 μW and the silicon area of the divider implemented is 79 μm2.

A comparative analysis of parallel SSHI and SEH for bistable vibration energy harvesters

The present work focuses on ambient vibration energy harvesting. Specifically, this article deals with bistable piezoelectric energy harvesters (PEHs) which exhibits a wider bandwidth than linear oscillators. These complex systems require an energy extraction circuit (EEC) to rectify their voltage to supply power to autonomous sensors. This EEC needs to be optimized in order to increase the harvested power and even the bandwidth of PEHs. Because of the complex dynamics of bistable PEHs, there is a lack of simple and physically-insightful models in the literature that would allow the understanding and optimization of the extraction circuit. To address this issue, the present work derives closed-form models of a bistable PEH coupled to a passive and an active synchronous EEC: respectively the standard energy harvesting (SEH) circuit and the parallel synchronized switch harvesting on inductor (P-SSHI) circuit. Experimental measurements conducted on a custom bistable PEH demonstrate the validity of the proposed models with a relative error lower than 15% on the harvested power and the bandwidth. The proposed models allow to easily understand the influence of the P-SSHI circuit on the dynamics of a bistable PEH. Moreover, a comparison of the performance of the SEH and the P-SSHI circuits, valid for any bistable generator, is proposed. The latter shows that under low electromechanical coupling and low acceleration amplitude the P-SSHI circuit leads to multiply the maximum harvested power up to 4.3 compared to the SEH circuit, and the bandwidth by a factor of 2.3.

A new multistable jerk chaotic system, its bifurcation analysis, backstepping control-based synchronization design and circuit simulation

A new multistable jerk chaotic system, its bifurcation analysis, backstepping control-based synchronization design and circuit simulation

Design Considerations of Multi-Phase Buck DC-DC Converter

The main objective of this article is to propose a rational methodology for designing multi-phase step-down DC-DC converters, which can find applications both in engineering practice and in power electronics education. This study discusses the main types of losses in the multi-phase synchronous buck converter circuit (transistors’ conduction losses, high-side MOSFET’s switching losses, reverse recovery losses in the body diode, dead time losses, output capacitance losses in the MOSFETs, gate charge losses in MOSFETs, conduction losses in the inductor, and losses in the input and output capacitors) and provides analytical dependencies for their calculation. Based on the control examples for applications characterized by low voltage and high output current, the multi-phase buck converter’s output and input current ripples are analyzed and compared analytically and graphically (3D plots). Furthermore, graphical results of the converter efficiency at different numbers of phases (N = 2, 4, 6, 8, and 12) are presented. An analysis of the impact of various parameters on power losses is conducted. Thus, a discussion on assessing the factors influencing the selection of the number of phases in the multi-phase synchronous buck converter is presented. The proposed systematized approach, which offers a fast and accurate method for calculating power losses and overall converter efficiency, reduces the need for extensive preliminary computational procedures and achieves optimized solutions. Simulation results for investigating power losses in 8-phase multi-phase synchronous buck converters are also presented. The relative error between analytical and simulation results does not exceed 4%.