Synchronous Link Research Articles

Performance Prediction of a Synchronization Link for Distributed Aerospace Wireless Systems

For reasons of stealth and other operational advantages, distributed aerospace wireless systems have received much attention in recent years. In a distributed aerospace wireless system, since the transmitter and receiver placed on separated platforms which use independent master oscillators, there is no cancellation of low-frequency phase noise as in the monostatic cases. Thus, high accurate time and frequency synchronization techniques are required for distributed wireless systems. The use of a dedicated synchronization link to quantify and compensate oscillator frequency instability is investigated in this paper. With the mathematical statistical models of phase noise, closed-form analytic expressions for the synchronization link performance are derived. The possible error contributions including oscillator, phase-locked loop, and receiver noise are quantified. The link synchronization performance is predicted by utilizing the knowledge of the statistical models, system error contributions, and sampling considerations. Simulation results show that effective synchronization error compensation can be achieved by using this dedicated synchronization link.

Echo-Domain Phase Synchronization Algorithm for Bistatic SAR in Alternating Bistatic/Ping–Pong Mode

When bistatic synthetic aperture radar (SAR) works in alternating bistatic/ping-pong mode, it can perform phase referencing without a synchronization link between different satellites. The key to this is to extract a compensation phase from the bistatic echoes, including oscillator phase differences. An echo-domain phase synchronization algorithm using the correlation of bistatic echoes is proposed. Because of its larger equivalent synchronization frequency, the echo-domain algorithm has higher phase synchronization accuracy than the algorithm in the image domain. Experiments using simulated bistatic echoes with real single-stripmap SAR echo validate the proposed echo-domain phase synchronization algorithm.

The data acquisition and transport design for NEMO Phase 2

Many high energy physics experiments (Auger, IceCube, NEMO, Km3Net) currently taking data or planned in the near future consist of big and sparse detectors that acquire a huge amount of data. This kind of topology requires the ability to acquire physics information in different places of the detector and correlate them using the occurrence time, usually with a sub-ns precision. The architecture described here provides a real-time data transport layer, used to implement the data acquisition system for the NEMO experiment, and consists of a synchronous link with fixed and deterministic latency. The system clock, distributed at every level of the apparatus, has been derived by the signals provided by a GPS receiver during the operating configuration. The aim of this contribution is to give an overview of the NEMO electronic system: the underwater electronics sample signals from photomultipliers and acquires slow-control data from both oceanographic instruments and dedicated sensors, allowing to monitor the operational conditions of the apparatus. The whole data are sent to the laboratory through a fully bi-directional fiber optic link. On-shore the data are received by dedicated boards that distribute them to the first-level trigger and to the slow-control system. A description of the different stages of data acquisition and transport will be given.

Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design

Source synchronous links for use in multi-synchronous networks-on-chip (NoCs) are becoming the most vulnerable points for correct network operation and must be safeguarded against intra-link delay variations and signal misalignments. The intricacy of matching link net attributes during placement and routing and the growing role of process parameter variations in nanoscale silicon technologies are the root causes for this. This article addresses the challenge of designing a process variation and layout mismatch tolerant link for synchronizer-based GALS NoCs by implementing a self-calibration mechanism. A variation detector senses the variability-induced misalignment between data lines with themselves and with the transmitter clock routed with data in source synchronous links. A suitable delayed replica of the transmitter clock is then selected for safe sampling of misaligned data. The manuscript proves robustness of the link in isolation with respect to a detector-less link, but also assesses integration issues with the downstream synchronizer and switch architecture, proving the benefits in a realistic experimental setting for cost-effective NoCs.

19.5: Unique Approach for Replacement Displays in Military Systems

AbstractLegacy military systems will continue to be around for years to come since funding for new systems is virtually nonexistent. Replacement products must be manufactured to meet form, fit, and function and be drop‐in replacements as modification to the platform cannot always be accommodated. Currently there are many “out‐of‐production” monochrome plasma, CRTs and electroluminescent displays in these systems. Sometimes products can be built around commercial off‐the‐shelf COTS LCD modules, but many times the only possible solution is a unique system made from a modified LCD. This paper addresses a unique approach to one such application starting with a 27 inch LCD panel cut to fit a product with outside dimensions of 26.75 inches wide by 8.427 inches high by 3.250 inches deep. The cut LCD results in a panel with resolution of 1920 × 400 lines which replaces an out of production neon‐orange AC plasma with a resolution of 1536 × 288 lines. The replacement system is programmed to interface via EIA 485 Synchronous Data Link SDLC type I/O and provides data to the screen in an orange color replicating the AC plasma color. The display system includes an infrared touch panel, a processor, and self contained power system. This paper will begin with the military application/specification and provide an overview of product design and test. The resized LCD was the only possible solution, it worked, and it's COTS.

Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links

High-speed links which employ source synchronous clocking architectures have the ability to track correlated jitter between clock and data channels up to high frequencies. However, system timing margins are degraded by channel skew between clock and data signals and high-frequency loss. This paper describes how these key channel effects impact the jitter performance and influence the clocking architecture of high-speed source synchronous links. Tradeoffs in complexity and jitter tracking performance of common per-channel de-skew circuits are discussed, along with how band-pass filtering can be leveraged to provide additional jitter filtering at the receiver. Jitter tolerance analysis for a 10 Gb/s system shows that a near all-pass delay-locked loop (DLL) and phase-interpolator- (PI-) based de-skew performs best under low skew conditions, while, at high skew, architectures which leverage band-pass clock filtering or a phase-locked loop (PLL) for increased jitter filtering are more suitable. De-skew based on injection-locked oscillators (ILOs) offer a reduced complexity design and competitive jitter tolerance over a wide skew range.

Wave-pipelined intra-chip signaling for on-FPGA communications

On-FPGA communication is becoming more problematic as the long interconnection performance is deteriorating in technology scaling. In this paper, we address this issue by proposing a novel wave-pipelined signaling scheme to achieve substantial throughput improvement in FPGAs. A new analytical model capturing the electrical characteristics in FPGA interconnects is presented. Based on the model, throughput and power consumption of a wave-pipelined link have been derived analytically and compared to the conventional synchronous links. Two circuit designs are proposed to realize wave-pipelined link using FPGA fabrics. The proposed approaches are also compared with conventional synchronous and asynchronous pipelining techniques. It is shown that the wave-pipelined approach can achieve up to 5.7 times improvement in throughput and 13% improvement in power consumption versus conventional delay-based on-chip communication schemes. Also, trade-offs between power, throughput and area consumption between the proposed and conventional designs are studied. The wave-pipelining approach provides a new alternative for on-FPGA communications and can potentially become a promising solution to mitigate the future interconnect scaling challenge.

High-Speed, Fixed-Latency Serial Links With FPGAs for Synchronous Transfers

Fixed-latency serial links find application in trigger and data acquisition systems of high energy physics (HEP) experiments requiring a predictable data transfer timing. In some architectures, there is the need to clock the data in and out from the link synchronously with a system clock (i.e., synchronous transfers) instead of using the clock recovered from the serial stream. In this work, we present a synchronous link architecture based on high-speed transceivers embedded in latest generation field programmable gate arrays (FPGAs). These transceivers are typically designed for applications that tolerate latency variations. However, we have developed two configurations and a clocking scheme to implement fixed-latency operation. The latency is constant during the transfer, after a loss of lock or a power cycle. Once locked, the link can be considered as a synchronous pipeline. The configurations do not depend on a particular serial encoding, the encoder/decoder being external to the transceiver. We discuss the latency performance for each configuration and show an implementation of the architecture we propose. We also present experimental results showing the stability of the latency of the link.

Adaptive Subcarrier Allocation in Synchronous Reverse Links of a Multicarrier CDMA System with Time and Frequency Spreading

Multicarrier code-division multiple access (CDMA) with time and frequency spreading has been recently considered as a candidate for fourth-generation (4G) wireless systems. This signaling scheme simultaneously utilizes code spreading in the time and frequency domains to simultaneously improve frequency diversity and minimize multiuser access interference. As a result, it is capable of outperforming multicarrier CDMA systems that employ 1-D spreading. In this paper, a novel adaptive subcarrier allocation algorithm is developed for multicarrier CDMA with time and frequency spreading to improve the overall bit error rate (BER) performance for all spreading configurations. This algorithm assigns users to subcarrier groups that provide favorable fading characteristics while simultaneously reducing the amount of interference caused to other users. The proposed algorithm is shown to provide a performance improvement, ranging from 1.5 dB with 2times16 (time times frequency) and spreading to 7 dB with 16times2 (time times frequency) spreading. The algorithm is also shown to maintain or improve the BER floor for each spreading configuration. It is concluded that at higher and lower levels of Eb/No, a higher frequency- and time-domain spreading should be, respectively, employed to improve BER performance. Furthermore, the Eb/No threshold level to switch between time and frequency spreading for the analyzed system is found to be 2.5 dB.

Test beam operation of the CMS calorimeter trigger synchronization boards

The CMS experiment uses information from its electromagnetic and hadronic calorimeters and muon detectors to decide whether to read out the whole detector. For such a task to be successful, all trigger primitives pushed through the trigger decision tree must be flawlessly aligned in time for operation at 40 MHz. Both calorimeters in CMS use the Synchronization Link Board for this purpose. In this article we report on the test results of this board using the bunched beams available in the H4 electron beam line at CERN.

Approach of Adaptive Synchronization for Bistatic SAR Real-Time Imaging

The use of a novel synchronization link to compensate time, phase, and spatial synchronization errors is proposed, aiming at the development of a practical synchronization technique for bistatic synthetic aperture radar (BiSAR) real-time imaging. With the proposed technique, an amplitude-modulated signal emitting from the transmitter is received by a passive receiver and divided into two channels. One is passed through an envelope detector and then used to trigger the sampling clock, and the second is used to achieve spatial synchronization and phase synchronization. Finally, the residual time synchronization errors are compensated with a proposed high-precision range realignment method, and the residual phase synchronization errors are compensated with autofocus algorithms. This technique allows a passive receiver, which is teamed with an illuminator at a safe standoff distance, to receive the data reflected from potentially hostile areas of interest. Thus, this configuration, making real-time imaging possible, has a particular value in military applications. Simulation results show that successful adaptive synchronization for BiSAR real-time imaging is possible by using this dedicated synchronization link.

TanDEM-X: A Satellite Formation for High-Resolution SAR Interferometry

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> TanDEM-X (TerraSAR-X add-on for Digital Elevation Measurements) is an innovative spaceborne radar interferometer that is based on two TerraSAR-X radar satellites flying in close formation. The primary objective of the TanDEM-X mission is the generation of a consistent global digital elevation model (DEM) with an unprecedented accuracy, which is equaling or surpassing the HRTI-3 specification. Beyond that, TanDEM-X provides a highly reconfigurable platform for the demonstration of new radar imaging techniques and applications. This paper gives a detailed overview of the TanDEM-X mission concept which is based on the systematic combination of several innovative technologies. The key elements are the bistatic data acquisition employing an innovative phase synchronization link, a novel satellite formation flying concept allowing for the collection of bistatic data with short along-track baselines, as well as the use of new interferometric modes for system verification and DEM calibration. The interferometric performance is analyzed in detail, taking into account the peculiarities of the bistatic operation. Based on this analysis, an optimized DEM data acquisition plan is derived which employs the combination of multiple data takes with different baselines. Finally, a collection of instructive examples illustrates the capabilities of TanDEM-X for the development and demonstration of new remote sensing applications. </para>

Performance Prediction of a Phase Synchronization Link for Bistatic SAR

Oscillator phase noise can dictate the performance of bistatic and multistatic synthetic aperture radar imaging. In this letter, the use of a dedicated synchronization link to quantify and compensate oscillator phase noise is investigated. Different synchronization schemes are presented, and their performance is analyzed. The error contribution of the synchronization link itself, which may suffer from receiver noise, aliasing, interpolation, and filter mismatch, is included in the analysis. The synchronization link performance is given in a frequency-domain closed integral form

A 48 channel pulse shape digitizer with DSP

A 48 channel, 40-65 MS/sec., 10 bit pulse shape digitizer card has been designed in the VME-6U form factor. The design uses 6 octal Flash Analog to Digital Converter (FADC) chips (ADS5121 or ADS5122) from Texas Instruments. The FADCs are read out by 6 Altera Cyclone FPGAs. A 7th FPGA is used to collect and merge the event fragments. The present firmware includes trigger latency buffers, waveform segment buffers, real-time digital filtering, time stamp generation, amplitude evaluation, event formatting and buffering, plus a simple VME A24D32 interface. The design also includes a source synchronous bi-directional serial LVDS link for the interconnection of the modules to a large system. The first version of the module is designed for an R&D test readout system connected to a few hundred drift chamber cathode pads or TPC cathode/anode pads. The final version is intended for the readout of the KOPIO preradiator cathode drift chamber pads (/spl sim/75000 channels). This version will only have the LVDS interconnect. The present design using off-the- shelf commercial components is an interesting alternative to an ASIC approach for intermediate size readout system. It occupies about 3 times the area of an equivalent ASIC system, and has comparable power dissipation. In its present form, the development version of the module can be useful as a general purpose waveform digitizer and DSP with its high density (48 channels per single width VME module) at a relatively low cost per channel.

Analysis of the Possibilities of the Usage of Electrical Synchronous Link for a CNC Gear Hobbing Machine

The method of creating the dynamical model of the CNC gear hobbing machine and for its analyzing is presented in this paper. The model comprises detail mechanical parts of the hob spindle and work spindle axes, their electrical counterparts, linking, and allows one to investigate dynamic characteristics of the machine and to simulate processes, which take place during gear hobbing. The article also presents the simulation diagram, introducing these axes and the third axis, which help to model the cutting process. It also presents results of simulation of processes during hobbing and amplitude-frequency characteristics calculated.

A framework for operations management: the value chain

Proposes that a broad perspective needs to be taken of operations management, so that it is no longer seen as the domain of mechanistic functionalism, but rather as the architect and engineer of the business model driving in turn the firm's creation of value. Suggests that a value chain approach provides an appropriate framework for such business model architecture. Draws a distinction between industry level value chains and value chain analysis at the level of the firm where the focus is on business processes. Suggests that mapping one against the other is critical to business model effectiveness and the creation of value. Finally, notes that a firm's value chain should not be seen as necessarily a series of smooth synchronous links, but as dynamic that creates its own interaction costs. This should not be seen as dysfunctional, but as a source of dynamism replicating the market environment the firm is operating in. While it does not sit well with the notions of scientific management so commonly associated with classical operations management, suggests that this process fusion is a fundamental aspect of the firm's operations that needs to be purposefully managed.

High-performance DRAMs in workstation environments

This paper presents a simulation-based performance study of several of the new high-performance DRAM architectures, each evaluated in a small system organization. These small-system organizations correspond to workstation-class computers and use only a handful of DRAM chips (/spl sim/10, as opposed to /spl sim/1 or /spl sim/100). The study covers Fast Page Mode, Extended Data Out, Synchronous, Enhanced Synchronous, Double Data Rate, Synchronous Link, Rambus, and Direct Rambus designs. Our simulations reveal several things: 1) Current advanced DRAM technologies are attacking the memory bandwidth problem but not the latency problem; 2) bus transmission speed will soon become a primary factor limiting memory-system performance; 3) the post-L2 address stream still contains significant locality, though it varies from application to application; 4) systems without L2 caches are feasible for low- and medium-speed CPUs (1 GHz and below); and 5) as we move to wider buses, row access time becomes more prominent, making it important to investigate techniques to exploit the available locality to decrease access time.

A novel high-power low-distortion synchronous link converter-based load compensator without the requirement of VAr calculator

A high-power low-distortion static VAr compensator based on a synchronous link converter has been proposed, where the harmonics are eliminated by incorporating a low-power insulated-gate-bipolar-transistor-based controlled current auxiliary converter in conjunction with a high-power gate-turn-off-thyristor-based converter. In this paper, a new load compensator based on this topology is proposed which does not require the information of the voltampere required by the load. As the requirement of the reactive voltampere calculator is eliminated, the scheme becomes insensitive to system frequency variations, temperature, and component aging. The control scheme required for the compensator is developed. The operation of the scheme is validated through extensive simulation studies. Experimental results obtained from a laboratory prototype are provided to demonstrate the viability of the scheme.

A simplified control strategy for a high-power low-distortion synchronous link converter VAr compensator

A high power low distortion static VAr compensator was proposed by the authors in 1997. The harmonics are eliminated by incorporating a low power IGBT based controlled current auxiliary converter in conjunction with a high power GTO based converter. The current reference required by the auxiliary converter is calculated by an involved procedure which makes the overall compensation process complicated. In this paper, a simplified control scheme for the VAr compensator is proposed. The effectiveness of the proposed scheme is investigated for a case where the VAr compensator is specifically used for load compensation and also for the case where it is used as a general purpose VAr generator. Detailed simulation studies of the schemes are presented. Experimental results obtained from a laboratory prototype are provided to demonstrate the viability of the proposed method.

A performance comparison of contemporary DRAM architectures

In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-based performance study of a representative group, each evaluated in a small system organization. These small-system organizations correspond to workstation-class computers and use on the order of 10 DRAM chips. The study covers Fast Page Mode, Extended Data Out, Synchronous, Enhanced Synchronous, Synchronous Link, Rambus, and Direct Rambus designs. Our simulations reveal several things: (a) current advanced DRAM technologies are attacking the memory bandwidth problem but not the latency problem; (b) bus transmission speed will soon become a primary factor limiting memory-system performance; (c) the post-L2 address stream still contains significant locality, though it varies from application to application; and (d) as we move to wider buses, row access time becomes more prominent, making it important to investigate techniques to exploit the available locality to decrease access time.