This paper presents the design and optimization of a 4-bit absolute value detector, focusing on enhancing circuit performance while minimizing delay and power consumption. A truth table was initially constructed to clearly understand the functionality of the detector. Logic expressions were simplified using Karnaugh maps, and the detector applied only NAND gates, NOR gates, and inverters. This approach not only improved the circuit's efficiency but also enabled the rapid identification of critical paths due to the design's high symmetry. The impact of input capacitance and supply voltage on delay and power consumption was analyzed. Increasing input capacitance reduced delay but increased overall power consumption, while decreasing supply voltage had the opposite effect. To further optimize performance, the internal capacitance of the last gate on the critical path was reduced, introducing a new set of constraints and power consumption equations. Minimum power consumption was calculated using MATLAB under the new constraints, resulting in a significant reduction compared to previous values. Experimental results demonstrated the effectiveness of the optimization strategy.
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