Symmetric Multiprocessor Research Articles

Software Drift

Since the systems have a common parent, they probably work in the same technical domain, and therefore the features and fixes that are going to be added are probably similar. KV happens to have an example case at hand: two operating systems that diverged before they added SMP (symmetric multiprocessing) support. When an operating system adds SMP to an existing kernel, the first thing we think of is locks, those handy-dandy little performance killers that we've all been sprinkling around our code since the end of Dennard scaling.

"Comparative Analysis of Energy Cost of Sequential and Parallel Cryptographic Algorithms on Different Platforms"

Cell phones, smart cards, and health monitoring gadgets are just a few examples of the numerous battery-powered embedded systems utilized to access, alter, and store sensitive and complicated data today. Users are concerned about the protection of their identity credentials, their software packages, and their information. These systems make considerable use of cryptographic algorithms to implement security measures. Many cryptographic algorithms do calculations that are hard to compute and waste a huge amount of energy as a result. In this study, the energy consumption of serial and parallel cryptography algorithms is analyzed. Using an eight-core parallel system and Joule metre (Microsoft's Research Tool), we were able to reduce energy consumption in comparison to sequential algorithms with promising results. The study says that low-frequency symmetric multiprocessors have shown promising results and can make a big difference in green computing, which would be good for society as a whole.

GPUOPT

On-chip photonics is a disruptive technology, and such NoCs are superior to traditional electrical NoCs in terms of latency, power, and bandwidth. Hence, researchers have proposed a wide variety of optical networks for multicore processors. The high bandwidth and low latency features of photonic NoCs have led to the overall improvement in the system performance. However, there are very few proposals that discuss the usage of optical interconnects in Graphics Processor Units (GPUs). GPUs can also substantially gain from such novel technologies, because they need to provide significant computational throughput without further stressing their power budgets. The main shortcoming of optical networks is their high static power usage, because the lasers are turned on all the time by default, even when there is no traffic inside the chip, and thus sophisticated laser modulation schemes are required. Such modulation schemes base their decisions on an accurate prediction of network traffic in the future. In this article, we propose an energy-efficient and scalable optical interconnect for modern GPUs called GPUOPT that smartly creates an overlay network by dividing the symmetric multiprocessors (SMs) into clusters. It furthermore has separate sub-networks for coherence and non-coherence traffic. To further increase the throughput, we connect the off-chip memory with optical links as well. Subsequently, we show that traditional laser modulation schemes (for reducing static power consumption) that were designed for multicore processors are not that effective for GPUs. Hence, there was a need to create a bespoke scheme for predicting the laser power usage in GPUs. Using this set of techniques, we were able to improve the performance of a modern GPU by 45% as compared to a state-of-the-art electrical NoC. Moreover, as compared to competing optical NoCs for GPUs, our scheme reduces the laser power consumption by 67%, resulting in a net 65% reduction in ED 2 for a suite of Rodinia benchmarks.

Safety Characteristic Evaluation of Cage in Cylindrical Roller Bearing at the Stage of Start-Up and Stop

The dynamics model of cylindrical roller bearing (CRB) in aeroengine main shaft was promoted and solved by Hilber–Hughes–Taylor (HHT) integer algorithm with variable step in combination with symmetric multiprocessing (SMP) parallel solving technology, and a finite element model of roller to cage contact was built. The dynamic characteristics of CRB at the stage of start-up and stop were analyzed firstly, and then, the collision forces between rollers and cage were used as the boundary conditions of the finite element model to discuss the influences of working conditions, structural parameters, and materials on the stress distribution and safety characteristic of cage at the stage of start-up and stop. The findings will provide the theoretical basis for the designing of CRB in aeroengine main shaft.

Toward a domain‐specific language for scientific workflow‐based applications on multicloud system

SummaryThe cloud computing paradigm has emerged as the backbone of modern price‐aware scalable computing systems. Many cloud service models are competing to become the leading doorway to access the computational power of cloud providers. Recently, a novel service model, called function‐as‐a‐service (FaaS), has been proposed, which enables users to exploit the cloud computational scalability, left out the configuration and management of huge computing infrastructures. This article discloses Fly, a domain‐specific language, which aims at reconciling cloud and high‐performance computing paradigms adopting a multicloud strategy by providing a powerful, effective, and pricing‐efficient tool for developing scalable workflow‐based scientific applications by exploiting different and at the same time FaaS cloud providers as computational backends in a transparent fashion. We present several improvements of the Fly language, as well as a new enhanced version of a source‐to‐source compiler, which currently supports Symmetric Multiprocessing, Amazon AWS, and Microsoft Azure backends and translation of functions in Java, JavaScript, and Python programming languages. Furthermore, we discuss a performance evaluation of Fly on a popular benchmark for distributed computing frameworks, along with a collection of case studies with an analysis of their performance results and costs.

Research on FFT Algorithm Use SMP System

Based on the theoretical research of a series of algorithms of adaptive beamforming and space-time adaptive processing, it is necessary to discuss the implementation of related algorithms on the machine hardware platform. Fast Fourier transform (FFT) is an essential process in this implementation. With the development of array antennas, the number of points to be calculated by the FFT has also increased significantly. Therefore, the ultra-large point FFT has become a key technology for current antenna signal processing. Most of the existing FFT algorithms are researched based on single-core processors, and there is very little literature on the research of super-large-point FFT algorithms suitable for Symmetric Multiprocessor (SMP). In this paper, through analyzing the characteristics of a symmetric multi-processor (SMP) parallel processing system, the very large FFT fast algorithm (VLFFT) is proposed. This algorithm significantly reduces the dependence on memory and improves the FFT's performance using the limited rules of the one-dimensional sequence split, changing the twiddle factor calculation method, and optimizing the data distribution and storage access. And the research's optimized very large FFT algorithms is also summarized in the paper. Experiment results show that the algorithm is suitable for the SMP platform and can effectively solve the problem of the very large FFT, which make single-core processors harder to realize.

Research on Identity Mechanism of Large-scale Drug Virtual Screening in Heterogeneous Multicore Environment and SMP Environment

This paper studies the mechanism of ultra-large-scale drug virtual screening in the heterogeneous multicore environment and SMP (Symmetric Multi-Processor) environment. Given the differences caused by different CPUs, we solved the incompatibility of the open-source molecular docking software Autodock Vina on two supercomputer systems in different environments and realized the automatic and intelligent large-scale virtual screening process for small-molecule ligands. At the same time, we propose a processing method of large-scale virtual screening using Autodock Vina in two environments, which makes full use of the dominant computing power of supercomputers to improve the efficiency of large-scale molecular docking and reduce the load of different supercomputer systems facing large-scale molecular docking tasks. Finally, we conduct a virtual screening experiment on the X86 platform supercomputer and the Sunway TaihuLight Supercomputer based on the heterogeneous multicore architecture CPU—SW26010. The experimental results show that our large-scale drug virtual screening method for different CPU environments is effective.

A Hardware Runtime for Task-Based Programming Models

Task-based programming models such as OpenMP 5.0 and OmpSs are simple to use and powerful enough to exploit task parallelism of applications over multicore, manycore and heterogeneous systems. However, their software-only runtimes introduce relevant overhead when targeting fine-grained tasks, resulting in performance losses. To overcome this drawback, we present a hardware runtime Picos++ that accelerates critical runtime functions such as task dependence analysis, nested task support, and heterogeneous task scheduling. As a proof-of-concept, the Picos++ hardware runtime has been integrated with a compiler infrastructure that supports parallel task-based programming models. A FPGA SoC running Linux OS has been used to implement the hardware accelerated part of Picos++, integrated with a heterogeneous system composed of 4 symmetric multiprocessor (SMP) cores and several hardware functional accelerators (HwAccs) for task execution. Results show significant improvements on energy and performance compared to state-of-the-art parallel software-only runtimes. With Picos++, applications can achieve up to 7.6x speedup and save up to 90 percent of energy, when using 4 threads and up to 4 HwAccs, and even reach a speedup of 16x over the software alternative when using 12 HwAccs and small tasks.

ON THE CONSTRUCTION OF A SOFTWARE ARCHITECTURE FORNUCLEAR SYSTEMS ON A CRYSTAL

The article discusses how to build software architecture for multi-core systems on a chip (SoC), based on asym-metric and symmetric multiprocessing, the hypervisor. Asymmetric multiprocessing is a port for several operating systems on physi-cally separate processor cores. In symmetric multiprocessing in systems with core isolation, one OS is launched on several cores. OS SMP-system is ported without user intervention with a growing number of cores. Since all cores are managed by a single OS, message transfer between cores can occur at the L1 data cache level, providing faster communication with less jitter. Kernel isola-tion allows you to reserve a kernel for a hard real-time application, protecting it from the influence of other high-performance ker-nels, which for the software architecture allows you to select your operating system without creating low-level software when man-aging multiple operating systems. The hypervisor refers to a low-level software system. It manages several independent operating systems that are at a higher level. Developing multi-core systems-on-chip offerings focused on the embedded market are well suited for asymmetric multiprocessing configurations. This architecture is useful for developers who use the performance of a real-time operating system in combination with a diverse set of Linux kernel functions. The article discusses the software and hardware solu-tions contained in the XAPP1079 environment, which are required to run Linux on a single Zynq-7000 All Programmable system on a chip, and open source applications on the second core. Designing systems based on systems on a chip for high-performance and аreal-time applications requires an optimal solution taking into account the factors: data transfer time; separation of the operating system. A system solution for high-performance and real-time applications using a symmetric multiprocessor processing architecture with kernel isolation provides low latency, jitter and real-time system operation, while maintaining software SoC scalability. Pro-grammable logic integrated circuits containing multi-core subsystems have an efficient architecture with symmetric multiprocessing of data to ensure a compromise between the actual data transfer time and the low latency of their processing. The advantages of using symmetric multiprocessing manifest themselves if the load is distributed among several resources. In this case, the time re-quired to complete the task is reduced. However, the performance gain brought about by a simple multiplication of the number of performers will not necessarily be linear. Some tasks should be performed only sequentially. Multi-core systems are able to process packages much more efficiently than single-core ones -but only if they are managed by optimized software. It is expedient to develop multi-core computing software, including an OS with support for symmetric and asymmetric multiprocessor data processing archi-tectures, an embedded hypervisor, high-speed packet processing modules, and an exhaustive set of tools for the entire cycle of multi-core computing systems. The results of such development will find application in multiprocessor supercomputers and server applica-tions, in terminal devices, access aggregators and basic devices -where the highest throughput is required.

Dynamic cloud resource management for efficient media applications in mobile computing environments

Single-instruction-set architecture (Single-ISA) heterogeneous multi-core processors (HMP) are superior to Symmetric Multi-core processors in performance per watt. They are popular in many aspects of the Internet of Things, including mobile multimedia cloud computing platforms. One Single-ISA HMP integrates both fast out-of-order cores and slow simpler cores, while all cores are sharing the same ISA. The quality of service (QoS) is most important for virtual machine (VM) resource management in multimedia mobile computing, particularly in Single-ISA heterogeneous multi-core cloud computing platforms. Therefore, in this paper, we propose a dynamic cloud resource management (DCRM) policy to improve the QoS in multimedia mobile computing. DCRM dynamically and optimally partitions shared resources according to service or application requirements. Moreover, DCRM combines resource-aware VM allocation to maximize the effectiveness of the heterogeneous multi-core cloud platform. The basic idea for this performance improvement is to balance the shared resource allocations with these resources requirements. The experimental results show that DCRM behaves better in both response time and QoS, thus proving that DCRM is good at shared resource management in mobile media cloud computing.

: Cost Based Hardware Optimization for Asymmetric Multicore Processors

Heterogeneous Multiprocessors (HMPs) are popular due to their energy efficiency over Symmetric Multicore Processors (SMPs). Asymmetric Multicore Processors (AMPs) are a special case of HMPs where different kinds of cores share the same instruction set, but offer different power-performance trade-offs. Due to the computational-power difference between these cores, finding an optimal hardware configuration for executing a given parallel program is quite challenging. An inherent difficulty in this problem stems from the fact that the original program is written for SMPs. This challenge is exacerbated by the interplay of several configuration parameters that are allowed to be changed in AMPs. In this work, we propose a probabilistic method named CHOAMP to choose the bestavailable hardware configuration for a given parallel program. Selection of a configuration is guided by a user-provided run-time property such as energy-delay-product (EDP) and CHOAMP aspires to optimize the property in choosing a configuration. The core part of our probabilistic method relies on identifying the behavior of various program constructs in different classes of CPU cores in the AMP, and how it influences the cost function of choice. We implement the proposed technique in a compiler which automatically transforms a code optimized for SMP to run efficiently over an AMP, eliding requirement of any user annotations. CHOAMP transforms the same source program for different hardware configurations based on different user requirement. We evaluate the efficiency of our method for three different run-time properties: execution time, energy consumption, and EDP, in NAS Parallel Benchmarks for OpenMP. Our experimental evaluation shows that CHOAMP achieves an average of 65, 28, and 57 percent improvement over baseline HMP scheduling while optimizing for energy, execution time, and EDP, respectively.

Enhancing the performance of process level redundancy with coprocessors in symmetric multiprocessors

Enhancing the performance of process level redundancy with coprocessors in symmetric multiprocessors

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4

The POWER9TM family of chips is fabricated in 14-nm silicon-on-insulator finFET technology using 17 levels of copper interconnect. The 695-mm2 24-core microprocessor features a new core based on an execution slice microarchitecture. The chip contains 8 billion transistors and has 120 MB of eDRAM L3 cache. The processor features an adaptive clock strategy to reduce timing margin needed during power supply droop events by embedding analog voltage-droop monitors that direct a digital phase-locked loop to immediately reduce clock frequency in response to a droop event. The scale-out chip IO subsystem supports up to 300-GB/s accelerator bandwidth using new 25-Gb/s links, 48 lanes of PCIeGen4 totaling 192 GB/s, eight ports of 2667 MT/s DDR4, and 256 GB/s of symmetric multiprocessor (SMP) interconnect. The scale-up chip adds additional SMP bandwidth and replaces the DDR4 memory interface with eight ports of differential memory interfaces with 230 GB/s of bandwidth resulting in 12.9 Tb/s of total off-chip bandwidth.

Study the Influential Factors in the Hit Rate of Cache Memory for a Multiprocessors System

This paper presents an analytical and deductive study at software and hardware level for a symmetric multiprocessors system. Basic influential factors in the performance as cache memory size, processors number, and coherence protocols of cache memories are defined and compared, and a different simulations and evaluations of multiple experimental values of these parameters have been carried out also. In order to speed up the parallel processing and to improve the performance for realizing the execution in real time, harmonious values of these factors are obtained as experimental results.

Shared Memory Multicore MicroBlaze System with SMP Linux Support

In this work, we present PolyBlaze, a scalable and configurable multicore platform for FPGA-based embedded systems and systems research. PolyBlaze is an extension of the MicroBlaze soft processor, leveraging the configurability of the MicroBlaze and bringing it into the multicore era with Linux Symmetric Multi-Processor (SMP) support. This work details the hardware modifications required for the MicroBlaze processor and its software stack to enable fully validated SMP operations, including atomic operation support, shared interrupts and timers, and exception handling. New in this work, we present a scalable and flexible memory hierarchy optimized for Field Programmable Gate Arrays (FPGAs), which manages atomic operations and provides support for future flexible memory hierarchies and heterogeneous systems. Also new is an in-depth analysis of key performance characteristics, including memory bandwidth, latency, and resource usage. For all system configurations, bandwidth is found to scale linearly with the addition of processor cores until the memory interface is saturated. Additionally, average memory latency remains constant until the memory interface is saturated; after which, it scales linearly with each additional processor core.

Prenaut: Design space exploration for embedded symmetric multiprocessing with various on-chip architectures

Abstract As embedded systems have evolved to appear in many different domains, symmetric multiprocessing (SMP) has been the design choice from low-end to high-end devices. In this paper we present Prenaut, a design space exploration method for finding the best on-chip SMP architectures given processor cores, Level 1, Level 2, and Level 3 caches. Unlike traditional design space exploration tools that are majorly concerned with optimizations in processor, memory and cache structures with a fixed on-chip architecture, Prenaut explores architectures that have not been considered in symmetric multiprocessing domain. These architectures consist of shared instruction caches between cores and heterogeneous cache topologies that feature bypassing a level in the cache hierarchy. The design idea behind Prenaut is to build a data oriented design space exploration method that exploits simulation data to its full extent rather than discarding it. Therefore, Prenaut uses simulation data and applies machine learning methods for estimating design parameters. This provides very rapid estimation of the Pareto set and guides designers through the overall system design process. The design space is pruned by topological clustering of design points which groups similar topologies and new simulation points are selected via an ordered look up table that prevents infeasible random jumps in the design space. For the selected benchmarks, Prenaut can estimate the Pareto set up to 147x faster and the clustering information can reduce the design space up to 82% in comparison with a state-of-the-art evolutionary algorithm.

An Efficient Parallel Krylov-Schur Method for Eigen-Analysis of Large-Scale Power Systems

An efficient parallel Krylov-Schur method is proposed for computing eigenvalues and eigenvectors related with oscillating modes of low damping for large-scale power systems. Improved restarting techniques are explained and demonstrated in details, which focus on a refined selection of kept subspace in contraction and a reliable mechanism of no missing target eigenvalues. Cayley and shift-invert transforms are used to decouple the computation of eigen-analysis and enable the proposed parallelization with a master-slave scheme. Based on the improved restarting techniques, the strategy for adaptive allocation of shifts and the coordination of parallel computing tasks, the proposed method is capable of computing a large number of eigen-pairs with satisfactory accuracy, convergence rate and parallel acceleration. The computational efficiency is validated by three test cases from real-world large-scale power systems on a symmetric multi-processing (SMP) computer.

비대칭적 임베디드 멀티코어 프로세서의 성능 연구

Recently, the multi-core processor architecture is widely adopted in the embedded processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multicore processors are known to score higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core embedded processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric embedded dual-core, quad-core, octa-core and hexadeca-core processors and compared with the symmetric ones of similar hardware budget using MiBench benchmarks as input.

The Effect of NUMA Tunings on CPU Performance

Non-Uniform Memory Access (NUMA) is a memory architecture for symmetric multiprocessing (SMP) systems where each processor is directly connected to separate memory. Indirect access to other CPU's (remote) RAM is still possible, but such requests are slower as they must also pass through that memory's controlling CPU. In concert with a NUMA-aware operating system, the NUMA hardware architecture can help eliminate the memory performance reductions generally seen in SMP systems when multiple processors simultaneously attempt to access memory.The x86 CPU architecture has supported NUMA for a number of years. Modern operating systems such as Linux support NUMA-aware scheduling, where the OS attempts to schedule a process to the CPU directly attached to the majority of its RAM. In Linux, it is possible to further manually tune the NUMA subsystem using the numactl utility. With the release of Red Hat Enterprise Linux (RHEL) 6.3, the numad daemon became available in this distribution. This daemon monitors a system's NUMA topology and utilization, and automatically makes adjustments to optimize locality.As the number of cores in x86 servers continues to grow, efficient NUMA mappings of processes to CPUs/memory will become increasingly important. This paper gives a brief overview of NUMA, and discusses the effects of manual tunings and numad on the performance of the HEPSPEC06 benchmark, and ATLAS software.

SMP 가상 머신의 I/O 지연 시간 감소를 위한 이벤트 라우팅 기법

According to the hypervisor scheduler, the vCPU (virtual CPU) operates under two states: the running state and the stop state. When the vCPU is in the stop state, incoming events are delayed until that vCPU's state changes to the running state. The latency in handling such events that are sent to the vCPU is regarded as the I/O latency. Since a SMP (symmetric multiprocessing) VM (virtual machine) incorporates multiple vCPUs, the event latency on a SMP VM can vary according to specific vCPU that receives the event. In this paper, we propose a new scheme named event routing that sends events according to the operation state of each vCPU to reduce the event latency on an SMP VM. We implemented the proposed event routing scheme in Xen ARM hypervisor and confirmed the reduction of I/O latency from measuring the network RTT (round trip time) and the TCP bandwidth under a variety of testing conditions. The network RTT decreases by up to 94% and the TCP bandwidth increases up to 35% when compare to native Xen ARM.