Symmetric Multiprocessor Research Articles

Large-eddy simulations on distributed shared memory clusters

The practicality of Large-eddy simulation (LES) of turbulent combustion, as is found in gas turbine engines, on clusters of commodity PC-based symmetric multi-processor (SMP) systems in 2-, 4-, and 8-way configurations has been investigated. Bandwidth demands from both memory and networking in the benchmark LES algorithm are shown to the primary performance inhibitors. Contention in the various SMP architectures tested is shown to compound these two hardware limitations. To investigate the ability of the parallel clustered systems, low-level hardware studies are conducted in conjunction with bench-marking of the LES application. The hardware tests focus on memory and communication contention under loads found in the LES algorithm. For comparison, the benchmarks are also applied to two industry leading high-performance super-computing architectures. It is found that contention in the 4- and 8-way SMP architecture studied here limits their applicability while the 2-way systems shows competitive performance and speed-up compared to its industry counter-parts. It is concluded that design-level combustion LES on clusters of commodity hardware, when equipped with sufficient memory and communication bandwidth, are a viable substitute for more expensive super-computing platforms.

PARALLEL COPYING GARBAGE COLLECTION USING DELAYED ALLOCATION

We present a new approach to parallel copying garbage collection on symmetric multiprocessor (SMP) machines appropriate for Java and other object-oriented languages. Parallel, in this setting, means that the collector runs in several parallel threads. Our collector is based on a new idea called delayed allocation, which completely eliminates the fragmentation problem of previous parallel copying collectors while still keeping low synchronization, high efficiency, and simplicity of collection. In addition to this main idea, we also discuss several other ideas such as termination detection, balancing the distribution of work, and dealing with contention during work distribution.

Parallel Processing of First Order Linear Recurrence on SMP Machines

In this paper, we propose a new algorithm that analyzes the data dependency pattern in the first-order linear recurrence (FOLR) and transforms it into algebraically equivalent expanded form so that it can be processed in parallel using the threads on symmetric multiprocessor (SMP) machines. The transformation aims to eliminate the data dependencies in the naive nested form of the FOLR. However, as this transformation may result in extra multiplication operations, our algorithm examines the immanent overhead of the expanded form of the FOLR and generates a new hybrid form of the FOLR. The hybrid form combines nested and appropriately expanded form in order to make it suitable for parallel processing. The parallel algorithm based on the hybrid form of the FOLR is analytically examined and tested through implementation on SMP machines. The implementation details, such as the workload balancing between processors and the optimization of cache performance, are also discussed. The experimental results show that the parallel algorithm based on the hybrid form of the FOLR considerably improves the performance on SMP machines that have three of more processors.

A Scalable Interconnection Network Architecture for Petaflops Computing

Extrapolating technology advances in the near future, a computer architecture capable of petaflops performance will likely be based on a collection of processing nodes interconnected by a high-performance network. One possible organization would consist of thousands of inexpensive, low-power symmetric multiprocessor (SMP) nodes. Each node will inject data into the interconnection network at a very large rate and consequently, the interconnect scheme is one of the most crucial design issues affecting system performance. This paper describes the 2D simultaneous optical multiprocessor exchange bus (2D SOME-Bus) which has the potential to become the basis of a high-end computer architecture capable of petaflops performance. It consists of N horizontal, N vertical 1D SOME-Bus networks, and N2 nodes. Each node is connected to one horizontal and one vertical 1D SOME-Bus. Each of N nodes connected to one 1D SOME-Bus has a dedicated broadcast channel and an input channel interface based on an array of N receivers monitoring all N channels and allowing multiple simultaneous broadcasts. In the 2D SOME-Bus, messages being broadcast on one Bus can be broadcast in a cut-through manner on one or more Buses in the other dimension. This paper describes the optoelectronic devices and technology which make the 2D SOME-Bus possible, and the network interface organization. It also presents simulation results which compare the performance of the 2D SOME-Bus, the 1D SOME-Bus, the crossbar and the torus under the message-passing paradigm.

A 600-MHz Single-Chip Multiprocessor With 4.8-GB/s Internal Shared Pipelined Bus and 512-kB Internal Memory

A 600-MHz single-chip multiprocessor, which includes two M32R 32-bit CPU cores , a 512-kB shared SRAM and an internal shared pipelined bus, was fabricated using a 0.15-/spl mu/m CMOS process for embedded systems. This multiprocessor is based on symmetric multiprocessing (SMP), and supports modified-exclusive-shared-invalid (MESI) cache coherency protocol. The multiprocessor inherits the advantages of previously reported single-chip multiprocessors, while its multiprocessor architecture is optimized for use as an embedded processor. The internal shared pipelined bus has a low latency and large bandwidth (4.8 GB/s). These features enhance the performance of the multiprocessor. In addition, the multiprocessor employs various low-power techniques. The multiprocessor dissipates 800 mW in a 1.5-V 600-MHz multiprocessor mode. Standby power dissipation is less than 1.5 mW at 1.5 V. Hence, the multiprocessor achieves higher performance and lower power consumption. This paper presents a single-chip multiprocessor architecture optimized for use as an embedded processor and its various low-power techniques.

MPI/OpenMP Hybrid Parallel Molecular Dynamics Simulation on SMP Cluster Architecture

The authors applied MPI/OpenMP hybrid parallel programming model to molecular dynamics (MD) for simulating a protein structure. In a symmetric multiprocessor (SMP) cluster architecture, it can be expected that the hybrid parallel programming model, which uses the message passing library such as MPI for inter-SMP node communication and the loop directives such as OpenMP for intra-SMP node parallelization, is the most effective one. In this study, the parallel performance of the hybrid style was compared with that of conventional flat parallel programming style, which uses only MPI. The computer environments used here are Hitachi SR8000/MPP placed at the University of Tokyo. When using 16 SMP nodes (128 PEs), it was observed that the parallel efficiency with the hybrid style was 90%, which was 15% higher than that of the flat-MPI for MD simulation of a protein with 33 402 atoms.

SMP計算機を用いた系統制御システムの高速性とリアルタイム性の実現

High performance and real-time capability are very important for control systems including load dispatching office systems with energy management system (EMS) functions. Parallel computing and very large memory (VLM) introduced by general purpose symmetric multi-processor (SMP) computers are required to achieve high-performance computing for EMS applications. However, a performance decline was observed on concurrent execution of EMS applications in our early evaluation. VLM may cause non-preemption and I/O inversion problems that interfere with real-time processing. The main issues addressed in this paper are: (1) adoption guidelines of SMP computers to achieve high performance and (2) design guidelines to realize real-time capability with VLM environment from practical points of view. The verification results show that performance can be improved by 2 times by selecting SMP computers appropriately and that real-time processing can be realized by the guidelines. The results of this study are used in the newly developed load dispatching office system that has been in practical operation.

3P092 SMP並列コンピュータを用いたブラウン動力学法によるタンパク質折り畳みの長時間シミュレーション(蛋白質 C) 物性 : 安定性、折れたたみなど)

3P092 SMP並列コンピュータを用いたブラウン動力学法によるタンパク質折り畳みの長時間シミュレーション(蛋白質 C) 物性 : 安定性、折れたたみなど)

Shared memory multiprocessor architectures for software ip routers

We propose new shared memory multiprocessor architectures and evaluate their performance for future Internet protocol (IP) routers based on symmetric multiprocessor (SMP) and cache coherent nonuniform memory access (CC-NUMA) paradigms. We also propose a benchmark application suite, RouterBench, which consists of four categories of applications representing key functions on the time-critical path of packet processing in routers. An execution driven simulation environment is created to evaluate SMP and CC-NUMA router architectures using this RouterBench. The execution driven simulation can produce accurate cycle-level execution time prediction and reveal the impact of various architectural parameters on the performance of routers. We port the FUNET trace and its routing table for use in our experiments. We find that the CC-NUMA architecture provides an excellent scalability for design of high-performance IP routers. Results also show that the CC-NUMA architecture can sustain good lookup performance, even at a high frequency of route updates.

Memory management for multi-threaded software DSM systems

When software distributed shared memory (SDSM) systems provide multithreading to exploit cluster of symmetric multiprocessors (SMPs), a challenge is how to preserve memory consistency in a thread-safe way, which is known as “atomic page update problem”. In this paper, we show that this problem can be solved by creating two independent access paths to a physical page and by assigning different access permissions to them. Especially, we propose three new methods using System V shared memory inter-process communication (IPC), a new mdup() system call, and a fork() system call in addition to a known method using file mapping. The main contribution of this paper is to introduce various solutions to the atomic page update problem and to compare their characteristics extensively. Experiments carried out on a Linux-based cluster of SMPs and an IBM SP Night Hawk system show that the proposed methods overcome the drawbacks of the file mapping method such as high initialization cost and buffer cache flushing overhead. In particular, the method using a fork() system call preserves the whole address space to the application.

Adapting a parallel sparse direct solver to architectures with clusters of SMPs

We consider the direct solution of general sparse linear systems baseds on a multifrontal method. The approach combines partial static scheduling of the task dependency graph during the symbolic factorization and distributed dynamic scheduling during the numerical factorization to balance the work among the processes of a distributed memory computer. We show that to address clusters of Symmetric Multi-Processor (SMP) architectures, and more generally non-uniform memory access multiprocessors, our algorithms for both the static and the dynamic scheduling need to be revisited to take account of the non-uniform cost of communication. The performance analysis on an IBM SP3 with 16 processors per SMP node and up to 128 processors shows that we can significantly reduce both the amount of inter-node communication and the solution time.

Towards an efficient single system image cluster operating system

The lack of a single system image Operating System (OS) for clusters restricts their use for parallel processing. We propose an approach for building an efficient single system image cluster operating system. The proposed system implements distributed services performing global and dynamic resource management to offer high performance, high availability and ease of use and programming. The programming API of the OS running on each cluster node is kept unmodified but the high level OS services can take benefit of all cluster resources. Our approach has been validated by a prototype based on Linux. Our prototype comprises of a limited kernel patch and a set of modules extending the kernel to implement the cluster distributed services. Existing applications running on symmetric multiprocessors (SMP) on top of Linux can be executed on top of our cluster OS without modification.

Shared virtual memory clusters: bridging the cost-performance gap between SMPs and hardware DSM systems

Although the shared memory abstraction is gaining ground as a programming abstraction for parallel computing, the main platforms that support it, small-scale symmetric multiprocessors (SMPs) and hardware cache-coherent distributed shared memory systems (DSMs), seem to lie inherently at the extremes of the cost-performance spectrum for parallel systems. In this paper we examine if shared virtual memory (SVM) clusters can bridge this gap by examining how application performance scales on a state-of-the-art shared virtual memory cluster. We find that: (i) The level of application restructuring needed is quite high compared to applications that perform well on a DSM system of the same scale and larger problem sizes are needed for good performance. (ii) However, surprisingly, SVM performs quite well for a fairly wide range of applications, achieving at least half the parallel efficiency of a high-end DSM system at the same scale and often much more.

Performance of a parallel mixed finite element implementation for fourth order clamped anisotropic plate bending problems in distributed memory environments

The paper deals with a parallel implementation of a mixed finite element method of solution of a fourth order elliptic partial differential equation which in the particular case of aniso-/ortho-/isotropic plate bending problems gives a simultaneous approximation to the bending moment tensor field Ψ=( ψ ij ) 1⩽ i, j⩽2 and the displacement field u. The parallel implementation has been done in Silicon Graphics Origin 3800, a 4 processor Intel Xeon Symmetric Multiprocessor and a beowulf cluster 1 Installed in Department of Mathematics, IIT Bombay. Funding provided by Department of Science and Technology, Ministry of Defence and Technology, Government of India. 1 of four Intel Pentium III PCs. The indefinite linear system obtained after discretization using mixed finite element method is solved in parallel using direct (Schur's Complement approach) and iterative method (using Argonne National Laboratory's PETSc package). The numerical results obtained and the time, speed-up comparisons for the direct method and iterative methods for a few interesting examples are also given.

GOTPM: a parallel hybrid particle-mesh treecode

We describe a parallel, cosmological N-body code based on a hybrid scheme using the particle-mesh (PM) and Barnes-Hut (BH) oct-tree algorithm. We call the algorithm GOTPM for Grid-of-Oct-Trees-Particle-Mesh. The code is parallelized using the Message Passing Interface (MPI) library and is optimized to run on Beowulf clusters as well as symmetric multi-processors. The gravitational potential is determined on a mesh using a standard PM method with particle forces determined through interpolation. The softened PM force is corrected for short range interactions using a grid of localized BH trees throughout the entire simulation volume in a completely analogous way to P 3 M methods. This method makes no assumptions about the local density for short range force corrections and so is consistent with the results of the P 3 M method in the limit that the treecode opening angle parameter, θ→0. The PM method is parallelized using one-dimensional slice domain decomposition. Particles are distributed in slices of equal width to allow mass assignment onto mesh points. The Fourier transforms in the PM method are done in parallel using the MPI implementation of the FFTW package. Parallelization for the tree force corrections is achieved again using one-dimensional slices but the width of each slice is allowed to vary according to the amount of computational work required by the particles within each slice to achieve load balance. The tree force corrections dominate the computational load and so imbalances in the PM density assignment step do not impact the overall load balance and performance significantly. The code performance scales well to 128 processors and is significantly better than competing methods. We present preliminary results from simulations run on different platforms containing up to N=1 G particles to verify the code.

Implementation of the EARTH programming model on SMP clusters: a multi‐threaded language and runtime system

AbstractThis paper describes the design and implementation of an Efficient Architecture for Running THreads (EARTH) runtime system for a multi‐processor/multi‐node cluster. The (EARTH) model was designed to support the efficient execution of parallel (multi‐threaded) programs with irregular fine‐grain parallelism using off‐the‐shelf computers. Implementing an EARTH runtime system requires an explicitly threaded runtime system. For portability, we built this runtime system on top of Pthreads under Linux and used sockets for inter‐node communication. Moreover, in order to make the best use of the resources available on a cluster of symmetric multi‐processors (SMP), this implementation enables the overlapping of communication and computation.We used Threaded‐C, a language designed to implement the programming model supported by the EARTH architecture. This language allows the expression of various levels of parallelism and provides the primitives needed to manage the required communication and synchronization. The Threaded‐C programming language supports irregular fine‐grain parallelism through a two‐level hierarchy of threads and fibers. It also provides various synchronization and communication constructs that reflect the nature of EARTH's fibers—non‐preemptive execution with data‐driven scheduling—as well as the extensive use of split‐phase transactions on EARTH to execute long‐latency operations. Copyright © 2003 John Wiley & Sons, Ltd.

SYMNET: an optical interconnection network for scalable high-performance symmetric multiprocessors.

We address the primary limitation of the bandwidth to satisfy the demands for address transactions in future cache-coherent symmetric multiprocessors (SMPs). It is widely known that the bus speed and the coherence overhead limit the snoop/address bandwidth needed to broadcast address transactions to all processors. As a solution, we propose a scalable address subnetwork called symmetric multiprocessor network (SYMNET) in which address requests and snoop responses of SMPs are implemented optically. SYMNET not only has the ability to pipeline address requests, but also multiple address requests from different processors can propagate through the address subnetwork simultaneously. This is in contrast with all electrical bus-based SMPs, where only a single request is broadcast on the physical address bus at any given point in time. The simultaneous propagation of multiple address requests in SYMNET increases the available address bandwidth and lowers the latency of the network, but the preservation of cache coherence can no longer be maintained with the usual fast snooping protocols. A modified snooping cache-coherence protocol, coherence in SYMNET (COSYM) is introduced to solve the coherence problem. We evaluated SYMNET with a subset of Splash-2 benchmarks and compared it with the electrical bus-based MOESI (modified, owned, exclusive, shared, invalid) protocol. Our simulation studies have shown a 5-66% improvement in execution time for COSYM as compared with MOESI for various applications. Simulations have also shown that the average latency for a transaction to complete by use of COSYM protocol was 5-78% better than the MOESI protocol. SYMNET can scale up to hundreds of processors while still using fast snooping-based cache-coherence protocols, and additional performance gains may be attained with further improvement in optical device technology.

A parallel 1-D FFT algorithm for the Hitachi SR8000

In this paper, we propose a high-performance parallel one-dimensional fast Fourier transform (FFT) algorithm on clusters of vector symmetric multiprocessor (SMP) nodes. The four-step FFT algorithm can be altered into a five-step FFT algorithm to expand the innermost loop length. We use the five-step algorithm to implement the parallel one-dimensional FFT algorithm. In our proposed parallel FFT algorithm, since we use cyclic distribution, all-to-all communication takes place only once. Moreover, the input data and output data are both in natural order. Performance results of one-dimensional power-of-two FFTs on clusters of pseudo-vector SMP nodes, Hitachi SR8000, are reported. We succeeded in obtaining performance of over 61 GFLOPS on a 16-node Hitachi SR8000/MPP.

Scalable scheduling for symmetric multiprocessors (SMP)

We present a task duplication-based scalable scheduling algorithm for Symmetric Multiprocessors (SMP), called S3MP (Scalable Scheduling for SMP), to address the problem of task scheduling. The algorithm pre-allocates network communication resources so as to avoid potential communication conflicts, and generates a schedule for the number of processors available in a SMP. This algorithm employs heuristics to select duplication of tasks so that schedule length is reduced/minimized. The algorithm can schedule the tasks of a directed acyclic graph (DAG) on to the processors of SMP with a worst case time complexity O( V 2), where V is the number nodes of the DAG. The performance of the S3MP algorithm has been observed by comparing the schedule length under various number of processors and the ratio of communication to computation cost. This algorithm also has been applied to some practical DAGs.

Parallel optical interconnection network for address transactions in large-scale cache coherent symmetric multiprocessors

The authors address the primary limitation of bandwidth demands for address transaction in future cache coherent symmetric multiprocessors (SMPs). As a solution, the authors propose a scalable address subnetwork called symmetric multiprocessor network (SYMNET) in which address requests and snoop responses of shared memory multiprocessors are implemented optically. As the address phase of the transaction is linked to the address bandwidth, which is the major bottleneck in SMPs, they focus only on the address subnetwork in this paper. SYMNET has the capability to pipeline address requests from successive processors, which results in increasing the available address bandwidth and lowering the latency of the network. An optical token is implemented to achieve mutual exclusion to the shared channel. This enables collisionless broadcast of multiple address requests. The simultaneous insertion of multiple address requests into the address subnetwork complicates cache coherence. A modified coherence protocol, called COSYM, was introduced to solve the coherence problem. The authors evaluated SYMNET with a subset of Splash-2 benchmarks running from 4-32 processors. Their simulation studies have shown 10%-67% improvement in execution time for various applications. It is also shown that the average latency for a transaction to complete using COSYM was 85% better than the electrical case. An overview of the proposed optical implementation of SYMNET is presented along with the theoretical power budget and bit-error rate analysis. This analysis shows that SYMNET can scale up to hundreds of processors while still using fast snoopy-based cache coherence protocols and that additional performance gains may be attained with further improvement in optical device technology.