Symmetric Lateral Bipolar Transistors Research Articles

Triple-sided charged plasma symmetric lateral bipolar transistor on SiGe-OI

A novel triple sided charged plasma (3SCP) device structure of a symmetric lateral bipolar transistor (SLBT) on silicon–germanium on insulator (SiGe-OI) is proposed. Charged plasma lateral bipolar transistor on SOI have many advantages especially in overcoming the thermal budget in addition to high gain and high speed for analog signal applications. In this paper we have carried out a systematic study of this novel 3SCP SLBT with uniform 0.3 Ge content in silicon and with linearly graded SiGe as the active device layer. With 3SCP SLBT having linearly graded SiGe as active device layer we were able to achieve a current gain > 104, fT > 200 GHz and fmax > 1130 GHz. We were able to demonstrate improvement in terms of current gain, fT and fmax by around 4.52, 2.55 and 2.07 times respectively with our novel design as compared to the conventional charged plasma symmetric lateral bipolar transistor (CP SLBT) having uniform 0.3Ge content in Silicon as active device layer. A complementary 3SCP symmetric lateral bipolar inverter with linearly graded SiGe as active device layer is also discussed for digital applications. The inverter shows switching voltage (VM) = 0.4616 V, low noise margin (NML) = 0.4302 V and high noise margin (NMH) = 0.4725 V when operated at 1.0 V.

Impact of substrate bias and dielectrics on the performance parameters of symmetric lateral bipolar transistor on SiGe-OI for mixed signal applications

In our strive to improve upon low power high speed devices for digital and mixed signal applications, Symmetric Lateral Bipolar Transistor has come out as a promising candidate and gained importance of late. Researchers in the field have shown improved performance parameters with this novel device for digital and analog applications. We investigate for the first time the impact of substrate bias for symmetric lateral bipolar transistor on Silicon Germanium on Insulator (SiGe-OI) with varying thickness of active device area (TSiGe), thickness of BOX layer (TBox) and k-values of dielectric BOX layer for analog/mixed signal applications. We optimize our design in terms of major performance parameters like gain and fT by varying parameters like TSiGe, TBox and k-values of dielectric BOX under substrate biased condition. We were able to achieve an improvement in gain and fT (in GHz) by almost 41.7% @ IC ˜ 1 μA/μm and 1.4% respectively by increasing the k-value of BOX from 3.9 to 22 with substrate bias. We studied for the first time complementary symmetric lateral bipolar (CSLB) inverter with the introduction of high-k BOX along with substrate bias for digital applications. The inverter shows a low noise margin (NML) and a high noise margin (NMH) of 0.45 V and 0.37 V respectively when operated at 1.0 V.

A Perspective on SOI Symmetric Lateral Bipolar Transistors for Ultra-Low-Power Systems

The reasons why state-of-the-art vertical bipolar circuits dissipate very high power are explained. The recent advent of SOI symmetric lateral bipolar transistors invites us to rethink bipolar as a high-speed but low-power technology. Integrated Injection Logic ( $\text{I}^{2}\text{L}$ ) and complementary bipolar (analogous to CMOS) circuits in SOI lateral bipolar offer huge design windows for power versus performance tradeoff, suggesting the possibility of ultra-low-power systems with embedded high-speed cores. $\text{I}^{2}\text{L}$ SRAM cells could be more than twice as dense as CMOS SRAM cells. The SOI substrate offers a fourth device terminal that can be used to induce narrow-gap-base HBT-like I–V characteristics, which should further improve the power-performance of circuits in SOI lateral bipolar. Fin-structure devices enable significant improvement in ${f} _{\max }$ for RF and high-frequency applications. The process technology for SOI lateral bipolar is compatible with CMOS. The Si-OI version is definitely much less complex than CMOS.

Symmetric Lateral Doping-Free BJT: A Novel Design for Mixed Signal Applications

A novel device structure of a symmetric lateral bipolar junction transistor (BJT) on silicon on insulator is presented with two distinctive approaches to induce charge carriers in the undoped silicon thin film. The metal workfunction engineering and electrostatic approaches are used to induce charge carriers in the emitter and collector regions of a BJT. Simulated electrical characteristics of both n-p-n and p-n-p BJT configurations show superior results compared with the thin-base symmetric lateral BJT and bipolar charge plasma transistor. The optimized design showed a peak current gain >180, $f_{t} > 280$ GHz, $f_{\textrm {max}} > 950$ GHz and $V_{A} > 3$ V. The circuit performance of the devices for primary digital applications, viz., complementary bipolar inverter and SRAM cell are discussed. Apart from this, the concept of reconfigurability is also presented, where the same device can be configured as n-p-n and p-n-p by changing the polarity of the applied potential across the polarity control terminals.

On the Base Current Components in SOI Symmetric Lateral Bipolar Transistors

The base current components in semiconductor on insulator symmetric lateral bipolar transistors are examined in detail to yield insight into the underlying device physics. For Si-OI devices, the base current component due to recombination in the quasineutral base is negligible, the component due to injection into the emitter has a weaker than 1/ $\textit{N}_{E}$ dependence because of the effect of heavy doping. The component due to recombination in the emitter–base diode space-charge region is associated with the fabrication process, and could be reduced to a negligible level with process optimization. For SiGe-OI devices, the effect of heavy doping appears to be less than for Si-OI devices. The result is higher maximum current gain for SiGe-OI devices than for comparably doped Si-OI devices.

A Perspective on Symmetric Lateral Bipolar Transistors on SOI as a Complementary Bipolar Logic Technology

Recently published reports suggest that symmetric lateral bipolar transistors on semiconductor-on-insulator (SOI) is CMOS compatible in fabrication process, and can be much denser than CMOS due to their much larger (5-10× larger) drive-current capability. When used in traditional bipolar circuits, SOI bipolar offers much lower power dissipation and/or much higher maximum speed. With both NPN and PNP devices of comparable characteristics, SOI lateral bipolar suggests the possibility of complementary bipolar (CBipolar) circuits in configurations analogous to CMOS. In this paper, the performance versus power dissipation of CBipolar circuits is examined using analytic equations. It is shown that for CBipolar to be superior to CMOS in both performance and power dissipation, narrow-gap-base heterojunction structures, such as Si emitter with Ge base or Si emitter with SiGe base, are required.

On the Device Design and Drive-Current Capability of SOI Lateral Bipolar Transistors

The SOI symmetric lateral bipolar transistor is uniquely suitable for operation at high injection currents where the injected minority carrier density in the base region is larger than the base doping concentration. Transistors operating in high-injection can achieve record-high drive currents on the order of 3-5 mA/μm. The commonly used Shockley diode and bipolar current equations are modified to be applicable for all injection levels. Excellent agreement is shown between measured and modeled currents for data at V BC = 0. A novel partially depleted-base design can further increase the drive current and the current gain, especially at low V BE .

On the Performance and Scaling of Symmetric Lateral Bipolar Transistors on SOI

The performance potential and scaling characteristics of thin-base SOI symmetric lateral bipolar transistors were examined using 1-D analytic equations for the currents and capacitances. The device can operate at collector current densities >100 mA/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and it scales similarly to CMOS in terms of density. The physical base width is scalable to less than 20 nm. Multiple devices of different specifications can be integrated on a chip. A sample design is shown to have f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> > 200 GHz, f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> >1 THz, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A</sub> > 4V, and a self gain of 60. A balanced design is shown to have 350-GHz <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fT</i> and 700-GHz <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VA</i> of 2.4 V, and a self gain of 20. These results are superior to those reported for 32 nm SOI CMOS. The results suggest a need to rethink bipolar circuit design. They also suggest opportunities for novel bipolar and BiCMOS circuits. The devices in high-speed Si-base bipolar circuits operate at about 1.0 V. The path toward 0.5 V bipolar circuits is to use semiconductors with smaller bandgap, such as Ge.