Symbolic Simulation Research Articles

Transverse Fluctuations and Their Effects on the Stable Functioning of Semiconductor Devices

Semiconductor plasma is often found in chaotic unpredictable motion which shows some anomalous behaviors providing multiple challenges to work with the instabilities in a semiconductor device. Experimental studies have shown that these instabilities give rise to fluctuations and azimuthal non-uniformities, which are usually present in the semiconductor. The energy fluctuations have also been observed in some of the cases. In this paper, we have obtained the fluctuations in velocity field by integrating the linearized governing hydrodynamic equations with RungeKutta method of order four (RK4). Then, we have come up with a mathematical formulation, where these fluctuations can be obtained from a KdV family equation with homotopy-assisted symbolic simulation. We have also obtained the relative velocity between the solitary structures for different parameters. Finally, by giving a detailed explanation of the behavior of semiconductor devices, we can study the usefulness of formulating the plasma waves in the various regime, and predict their characteristics theoretically.

Homotopy Study of Spherical Ion-Acoustic Waves in Relativistic Degenerate Galactic Plasma

In this work, we start with the ion-acoustic waves in galactic plasma with the degenerate matter. We use the reductive perturbation technique to derive the spherical Kadomtsev–Petviashvili (SKP) equation. We next employ homotopy-aided symbolic simulation (HASS) to study the evolution of the spherical solitary wavefront. We compare the results obtained by HPM and RPT. To understand how the system behaves, we transform the evolutionary equations into a dynamical system. The phase portraits and the superperiodic waves reflect on the intricate processes within the plasma and determine the stability criteria and possible situations of chaos. The work will find applications in many astrophysical observations, such as electrostatic wave modes, gamma-ray bursts, and double-layer solitons. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PACS</i> —95.30.Qd, 52.65.-y, 52.35.-g, 52.35.Tc.

Stationary Structures in a Four Component Dense Magnetoplasma With Lateral Perturbations

We considered a dense plasma containing electrons, positrons, ions and dust particles in background magnetic and gravitational fields alongside collisional effects for the heavier species (ions and dust particles). Such plasmas are found in magnetars, black hole accretion disks, and so on. The quantum hydrodynamic (QHD) model was used to construct the governing equations of the plasma. Relativistic degeneracy pressure is taken as the equation of state for the electrons and positrons. Effects of exchange-correlation potential were also considered for the lighter species. We employed the reductive perturbation method (RPM) in order to obtain the Zakharov–Kuznetsov (ZK) equation describing 3-D ion acoustic waves (IAWs) with minimal lateral perturbations. Low order analytical solutions allow us to understand the parametric dependence of said structures. Our newly developed numerical technique: homotopy assisted symbolic simulation (HASS) sheds light on the gradual evolution of higher order stationary formations in the system. The results thus obtained can potentially explain certain astrophysical phenomena as well as dense laboratory plasmas.

Grammar-based fuzz testing for microprocessor RTL design

Recently, agile hardware design (AHD) methodology has been proposed to alleviate the productivity crisis brought by the growing complexity of modern microprocessor design. One of the key techniques in AHD is the adoption of hardware construction languages (HCLs) which have greatly improved the design productivity. However, the adoption of HCLs arises new challenges to design verification. In this paper, we proposed an enhanced coverage-directed dynamic verification technique for microprocessor RTL designs modeled using PyRTL HCL. The intention of the proposed method is to achieve higher coverage in dynamic verification.The proposed method is a hybrid between symbolic simulation and grammar-based fuzz testing, which offsets the disadvantages of each separate technique. We define Full Multiplexer Toggle Coverage (FMTC) to trace and provide feedback to the verification process. The achievement of high coverage is obtained by interleaving symbolic simulation and grammar-based fuzz testing passes. The symbolic simulation pass is used to generate tests that direct the testing to untouched corners, while the grammar-based fuzz testing pass is used to leverage test generation tasks and to enable the method to deal with microprocessor designs with a specific instruction set architecture (ISA). In addition, to further reduce testing cost, we propose a test compression technique to compress the generated test instructions by dropping redundant instructions.Finally, we implement all the enhancements in a test generation tool, named MPFuzz. Experimental results show that MPFuzz can efficiently generate test instructions for microprocessor RTL designs. The test instructions generated by MPFuzz can achieve higher coverage at least four times than that by the state-of-the-art fuzzing-based RTL test generation tool.

ProbNV: probabilistic verification of network control planes

ProbNV is a new framework for probabilistic network control plane verification that strikes a balance between generality and scalability. ProbNV is general enough to encode a wide range of features from the most common protocols (eBGP and OSPF) and yet scalable enough to handle challenging properties, such as probabilistic all-failures analysis of medium-sized networks with 100-200 devices. When there are a small, bounded number of failures, networks with up to 500 devices may be verified in seconds. ProbNV operates by translating raw CISCO configurations into a probabilistic and functional programming language designed for network verification. This language comes equipped with a novel type system that characterizes the sort of representation to be used for each data structure: concrete for the usual representation of values; symbolic for a BDD-based representation of sets of values; and multi-value for an MTBDD-based representation of values that depend upon symbolics. Careful use of these varying representations speeds execution of symbolic simulation of network models. The MTBDD-based representations are also used to calculate probabilistic properties of network models once symbolic simulation is complete. We implement the language and evaluate its performance on benchmarks constructed from real network topologies and synthesized routing policies.

FIVER – Robust Verification of Countermeasures against Fault Injections

Fault Injection Analysis is seen as a powerful attack against implementations of cryptographic algorithms. Over the last two decades, researchers proposed a plethora of countermeasures to secure such implementations. However, the design process and implementation are still error-prone, complex, and manual tasks which require long-standing experience in hardware design and physical security. Moreover, the validation of the claimed security is often only done by empirical testing in a very late stage of the design process. To prevent such empirical testing strategies, approaches based on formal verification are applied instead providing the designer early feedback.In this work, we present a fault verification framework to validate the security of countermeasures against fault-injection attacks designed for ICs. The verification framework works on netlist-level, parses the given digital circuit into a model based on Binary Decision Diagrams, and performs symbolic fault injections. This verification approach constitutes a novel strategy to evaluate protected hardware designs against fault injections offering new opportunities as performing full analyses under a given fault models.Eventually, we apply the proposed verification framework to real-world implementations of well-established countermeasures against fault-injection attacks. Here, we consider protected designs of the lightweight ciphers CRAFT and LED-64 as well as AES. Due to several optimization strategies, our tool is able to perform more than 90 million fault injections in a single-round CRAFT design and evaluate the security in under 50 min while the symbolic simulation approach considers all 2128 primary inputs.

Nonlinear interaction of intense laser beam with dense plasma

We studied the nonlinear evolution of an amplitude-modulated envelop soliton formed in a dense plasma when a laser beam interacts with it. The employment of our newly developed technique, homotopy-assisted symbolic simulation, has been instrumental in the study of the nature and formation of envelope solitons and their dependence on various parameters. The different orders of homotopy perturbation generate a convergent series solution for such nonlinear coupled partial differential equations (PDE). Our technique bypasses the rigorous analytical derivation of coupled PDE without a loss of information. The methodology is very novel and holds promise for application in models that explain experimental observations. The results will be beneficial in interpreting various dense laser plasma interactions.

A Path-Based Equivalence Checking Method Between System Level and RTL Descriptions Using Machine Learning

The growing complexity of modern digital design makes designers shift toward starting design exploration using high-level languages, and generating register transfer level (RTL) design from system level modeling (SLM) using high-level synthesis tools or manual transformation. Unfortunately, this translation process is very complex and error prone. The most important verification task is to check whether the RTL implementation is indeed equivalent to the system-level model. Equivalence checking is critical to ensure that the synthesized RTL conforms to its SLM specification. In this paper, we propose a novel path-based sequential equivalence checking method to validate the transformed RTL description against its corresponding SLM description. We represent the original SLM and the transformed RTL descriptions using Finite state machines with datapath (FSMD) and compare the path-pairs of the FSMD to obtain the equivalence of the designs. Then we recognize the corresponding path-pairs from all the generated paths of FSMD with Machine learning (ML) technique, and compare the recognized path-pairs by symbolic simulation and a satisfiability modulo theories (SMT) solver. Our method can handle designs without mapping information and improve the efficiency of the state-of-the-art path-based equivalence checking methods. The promising experiments on representative benchmarks indicate the efficiency and effectiveness of our method.

Amplitude modulation and soliton formation of an intense laser beam interacting with dense quantum plasma: Symbolic simulation analysis

AbstractIn this theoretical study, we investigate the amplitude modulation and envelop soliton formation in a dense plasma when such a plasma interacts with a strong laser beam. We have made use of the symbolic simulation technique to find the modulation instability of an electrostatic wave with higher orders of non‐linearity. We identified the range of wavenumber in which such non‐linearity is important. Furthermore, we have analysed the formation of envelope soliton of waves localized in space. The results obtained here will be helpful in interpreting different phenomena that arise in laser plasma interaction. The importance of the relativistic contribution of streaming particles is discussed alongside the parametric influences experienced by the plasma particles.

Automatic generation of assertions for detection of firmware vulnerabilities through alignment of symbolic sequences

Symbolic simulation of firmware allows to automatically find execution paths triggering undesired behaviors that could hide vulnerabilities. However, once an unexpected behavior is identified, understanding its origin is an even more challenging task for the verification engineer. While several static and dynamic tools exist for detecting vulnerabilities, the same is not true for identifying their causes. This article is intended to fill in the gap by proposing an automatic framework for catching the source of IP vulnerabilities. Given an unwanted behavior, in the form of a propositional logic assertion, the framework exploits symbolic simulation and a sequence alignment algorithm to generate a set of temporal assertions that represent the minimum sequence of firmware instructions necessary for triggering the related vulnerability. In this way, the designer can effectively identify the cause of the vulnerability and fix it. Experimental results show the efficacy of the methodology in terms of efficiency and effectiveness.

Formal Equivalence Checking Between System-Level and RTL Descriptions without Pre-Given Mapping Information

The growing complexity of digital designs makes it harder to discover inconsistency between system-level model (SLM) and register transfer-level (RTL) model. Equivalence checking is a promising solution to verify that the RTL description meets the requirements of the corresponding SLM description. However, the previously proposed formal equivalence checking approaches cannot handle designs if the mapping information is not given beforehand. Deep state sequences (DSSs)-based equivalence checking approach is the state-of-the-art equivalence checking approach based on Finite State Machines with Data Paths (FSMDs). But previously proposed DSS-based equivalence checking approach compared all the path-pairs blindly without pre-given mapping information, which wasted most verification efforts on useless comparisons. This paper proposes a novel DSS-based equivalence checking approach which can handle designs without pre-given mapping information and improve verification efficiency. Simulation technique is first used in our approach to generate mapping information of paths between SLM and RTL. With the generated mapping information, our approach can handle designs without pre-given mapping information. Only the generated corresponding path-pairs need to be compared by symbolic simulation, which improves the verification efficiency without blind comparisons. The experimental results show that the proposed approach can handle designs without pre-given mapping information and improve the efficiency of equivalence checking.

Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation

Formal verification of high-level SystemC designs is an important and challenging problem. One has to deal with the full complexity of C++ to extract a suitable formal model (front-end problem) and then, with large cyclic state spaces defined by symbolic inputs and concurrent processes. This paper describes a scalable and efficient stateful symbolic simulation approach for SystemC that combines state subsumption reduction (SSR) with partial order reduction (POR) and symbolic execution (SymEx) under the SystemC simulation semantics. While the SymEx+POR combination provides basic capabilities to efficiently explore the state space, SSR prevents revisiting symbolic states and therefore makes the verification complete. The approach has been implemented on top of an intermediate verification language for SystemC to address the front-end problem. The scalability and efficiency of the implemented verifier is demonstrated using an extensive set of experiments.

Automatic Correction of Dynamic Power Management Architecture in Modern Processors

The increasing demand for lower power forces designers to use sophisticated power management strategies such as multivoltage and power gating which are often accompanied with many design bugs. Correcting such bugs can be a time-consuming process that requires considerable manual efforts. In this paper, we propose a scalable automated method for correcting dynamic power management architectures by an incremental SAT-based mechanism. First, an initial counterexample (CEX) is generated by checking the equivalency between the specification model of the processor and its buggy implementation model. Then, we find two candidate solutions instead of one to satisfy this CEX. If two solutions are not equivalent, we generate new CEX in an iterative process which effectively converges into the final solution. The proposed method enables designers to correct multiple bugs such as missing isolation cells between two power domains, disordering in the sequence of control signals, error in the data restoring or saving, and powering off in always-on domains which are not addressed by existing methods. We have shown the effectiveness of our method on modern processors supporting complex power management mechanisms. The results confirm that our proposed method, respectively, reduces symbolic simulation steps and runtime by 2.33× and 47.93× compared to the state-of-the-art methods.

Two methods of decomposition symbolic simulation of circuit functions

A decomposition method of total algebraic complements with “screening” and the topology transformation method have been proposed for symbolic simulation of circuit functions. They are based on decomposition of the simulated circuit and the use of index operations in calculating the model matrix determinant and algebraic complements of its elements.

Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving

Test generation for hard-to-reach states is important in functional verification. In this paper, we present a path constraint solving-based test generation method (PACOST) which operates in an abstraction-guided semiformal verification framework to cover hard-to-reach states. PACOST combines concrete simulation and symbolic simulation on the design under verification for path constraint extraction and mutation, and uses a sequential path constraint extractor to generate a set of valid input vectors for exploring different simulation paths with different next states. It then works on a target state-oriented abstract model to select the next state with the smallest abstract distance. In addition, the value of register variables in control logic can be controlled by analyzing the data dependence between variables, which helps the simulation converge to the target states. Experimental results show that PACOST can generate shorter traces reaching hard-to-reach states, in comparison with previous abstraction-guided semiformal methods.

A Symbolic Simulator Platform for the Static Analysis of Thin Plates

The integration of symbolic capabilities into a simulation platform devoted to the analysis of thin plates can provide a greater flexibility in the learning process as it enables to incorporate, to experiment and simulate more complex and user-defined characteristics. With the present work one has built a symbolic simulator for the study of the mechanical behavior of thin plates. These plates, with a rectangular/square basis geometric configuration, are simply supported along its four edges, and can be made from homogeneous or non-homogeneous materials. The capabilities of this platform are briefly illustrated through an illustrative case study.

Workshop on Large Scale Computational Physics LSCP 2016

The LSCP workshop focuses on symbolic and numerical methods and simulations, algorithms and tools (software and hardware) for developing and running large-scale computations in physical sciences. Special attention goes to parallelism, scalability and high numerical precision. System architectures are also of interest as long as they are supporting physics-related calculations, such as: massively parallel systems, GPUs, many-integrated-cores, distributed (cluster, grid/cloud) computing, and hybrid systems. Topics this year are from theoretical physics (high energy physics and lattice gauge theory/QCD). The effects of transformations in obtaining numerical results for Feynman loop integrals, and the deployment of a novel architecture to achieve large computational power with low electric power consumption are presented.

Automatic Generation of Alternative Starting Positions for Simple Traditional Board Games

Simple board games, like Tic-Tac-Toe and CONNECT-4, play an important role not only in the development of mathematical and logical skills, but also in the emotional and social development. In this paper, we address the problem of generating targeted starting positions for such games. This can facilitate new approaches for bringing novice players to mastery, and also leads to discovery of interesting game variants. We present an approach that generates starting states of varying hardness levels for player 1 in a two-player board game, given rules of the board game, the desired number of steps required for player 1 to win, and the expertise levels of the two players. Our approach leverages symbolic methods and iterative simulation to efficiently search the extremely large state space. We present experimental results that include discovery of states of varying hardness levels for several simple grid-based board games. The presence of such states for standard game variants like 4 x 4 Tic-Tac-Toe opens up new games to be played that have never been played as the default start state is heavily biased.

Symbolic mathematics-based simulation of cylinder spaces for regenerative gas cycles

Regenerative gas cycles, including the Stirling engine, are sealed machines using pistons within cylinders to transfer energy from a heat source to a colder reservoir using a gas as working substance. For the optimal design of these cycles, we need a detailed description of gas dynamic behavior. This contribution deals with the simulation of cylinder spaces without internal combustion (as we find for regenerative gas cycles). For the simulation, we suggested a symbolic mathematics-based strategy to describe the dynamic system behavior based on partial non-linear differential equations for the conserved quantity. The renunciation of numerical approximation gives the advantage that the underlying physical mechanisms are characterized by exact expressions and parameters. Using some assumptions, the dynamic behavior of the gas within the cylinder is already described by ordinary non-linear differential equations. Depending on the selected boundary conditions analytical solutions can be obtained for some cases. Finally, the developed solution is based on it and will be received as a series expansion. Additionally, for the simulation-based optimization of the processes it is possible to calculate directly the periodical-steady state of the system with the help of the symbolic solution. The simulation is suitable for fundamental theoretical investigations, as well as for the implementation in simulation software for different regenerative gas cycles.

Efficient testing of multi‐output combinational cells in nano‐complementary metal oxide semiconductor integrated circuits

This study addresses the problem of efficient fault simulation and test generation in circuits using multi-output combinational logic cells. A symbolic fault simulation algorithm is proposed to exploit bit-level parallelism in order to represent the propagation of the output value of faulty cells throughout the circuit, thus accounting for different faulty behaviours in a single simulation step. A satisfiability (SAT)-based test generation procedure is also provided and it early discovers sets of undetectable behaviours. Results for a set of combinational benchmarks show the feasibility of the proposed approach.