Formal Equivalence Checking Between System-Level and RTL Descriptions without Pre-Given Mapping Information

Abstract

The growing complexity of digital designs makes it harder to discover inconsistency between system-level model (SLM) and register transfer-level (RTL) model. Equivalence checking is a promising solution to verify that the RTL description meets the requirements of the corresponding SLM description. However, the previously proposed formal equivalence checking approaches cannot handle designs if the mapping information is not given beforehand. Deep state sequences (DSSs)-based equivalence checking approach is the state-of-the-art equivalence checking approach based on Finite State Machines with Data Paths (FSMDs). But previously proposed DSS-based equivalence checking approach compared all the path-pairs blindly without pre-given mapping information, which wasted most verification efforts on useless comparisons. This paper proposes a novel DSS-based equivalence checking approach which can handle designs without pre-given mapping information and improve verification efficiency. Simulation technique is first used in our approach to generate mapping information of paths between SLM and RTL. With the generated mapping information, our approach can handle designs without pre-given mapping information. Only the generated corresponding path-pairs need to be compared by symbolic simulation, which improves the verification efficiency without blind comparisons. The experimental results show that the proposed approach can handle designs without pre-given mapping information and improve the efficiency of equivalence checking.