Switching Latency Research Articles

HyDMA: low-latency inter-core DMA based on a hybrid packet-circuit switching network-on-chip

With a growing number of cores integrated in a single chip, the efficiency of inter-core direct memory access (DMA) transfers has an increasingly significant impact on the overall performance of parallel applications running on network-on-chip (NoC) processors. In this paper we propose HyDMA, a low-latency inter-core DMA approach based on a hybrid packet-circuit switching NoC. With dynamic setup and lengthening of circuit channels composing of bidirectional links, HyDMA can achieve both high flexibility of packet switching and low communication latency of circuit switching for concurrent DMA transfers. Experimental results prove HyDMA exhibits high efficiency with marginal hardware overhead.

Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing

A field-assisted spin-torque transfer magnetoresistive RAM (STT-MRAM) cache is presented for the use in high-performance energy-efficient microprocessors. Adding field assistance reduces the switching latency by a factor of 4. An array model is developed to evaluate the switching energy for different field currents and array sizes. Several STT-MRAM-based cells demonstrate a 55% energy reduction as compared with an SRAM cache subsystem. As compared with STT-MRAM caches with subbank buffering and differential writes, a field-assisted STT-MRAM cache improves the system performance by 28%, with a 6.7% increase in energy.

Design and Experimental Evaluation of a Database-Assisted V2V Communications System Over TV White Space

Automakers are increasingly employing wireless communications technologies into vehicles, which are expected to be one of the primary tools to improve traffic flow and traffic safety. Anticipating a significant increase in the accompanying spectrum and capacity requirements, in this paper, we speculate about using dynamic spectrum access in general, and TV white space in particular for vehicular communications. To this end, we describe the concept, design, general architecture and operation principles of a vehicle-to-vehicle communications system over TV white space. This system makes dual use of a geolocation database and spectrum sensing to understand spectrum vacancies. In this architecture, whenever a database query result is available, that information is prioritized over sensing results and when the database access is disrupted, vehicles rely on the spectrum sensing results. After describing the general concepts, we numerically analyze and evaluate the benefits of using proxy vehicles for geolocation database access. Finally, we present the middleware-centric implementation and field test results of a multi-hop vehicle-to-vehicle communications system over the licensed TV-band. We present results regarding multi-hop throughput, delay, jitter, channel switching and database access latencies. This study complements our previous work which described spectrum sensing based vehicle-to-vehicle communications design and testing.

Performance Analysis of a Hybrid Optical–Electronic Packet Switch Supporting Different Service Classes

As a solution to the high energy consumption caused by numerous optical–electrical–optical (O-E-O) conversions in electronic switches, and the poor contention handling of all-optical switches, we investigated a hybrid switch that supplements optical switching with an electronic buffer. Our study takes into account reliable, fast, and default packets that have different requirements of quality-of-service performance criteria. We show, by simulations, that with only a few electronic ports to the buffer, the hybrid switch significantly improves the packet loss rates and the sustainable system load compared to an all-optical bufferless switch and meets the different packet classes’ requirements. In addition, we quantified the considerable decrease of O-E-O conversions as well as the switching latency achieved by the hybrid switch compared to an electronic switch.

A High-Radix, Low-Latency Optical Switch for Data Centers

We demonstrate an optical switch design that can scale up to a thousand ports with high per-port bandwidth (25 Gbps+) and low switching latency (40 ns). Our design uses a broadcast and select architecture, based on a passive star coupler and fast tunable transceivers. In addition we employ time division multiplexing to achieve very low switching latency. Our demo shows the feasibility of the switch data plane using a small testbed, comprising two transmitters and a receiver, connected through a star coupler.

Measurement of Switching Latency in High Data Rate Ethernet Networks

The paper deals with a methodology of switching latency measurement in switched Ethernet networks. The switching latency is parameter necessary for simulation and design of low-latency networks that are often intended for real-time control inherent to many industrial applications. The proposed measurement methodology provides a simple way of switching the latency determination and vendor quoted latency values verification directly at the physical layer. Numerous experimental measurements were carried out to support the arguments in this paper and to demonstrate the usability of the proposed methodology. All results are presented and analysed up to 10GBase-R Ethernet including OpenFlow switches. DOI: http://dx.doi.org/10.5755/j01.eee.21.3.10445

IPTV channel switching delay reduction through predicting subscribers’ behaviors and preferences

This article aims at proposing a novel approach based on subscribers' behaviors and preferences in order to reduce channel switching delay in Internet protocol television (IPTV) over WiMAX networks. In the proposed scheme, first an algorithm is proposed for extracting users' preferences according to their behaviors so that the list of favorite channels is established for each user, where each channel is assigned a score. Having the channels clustered by the IPTV service providers, we propose two algorithms namely PGCP and P-PGCP based on which the favorite channels whose scores exceed a predefined threshold are pre-fetched in a low quality format. This procedure referred to as background channel transmission is the key idea in reducing channel switching latency. In PGCP, the dedicated bandwidth of pre-fetched channels is given to the highest score channels available at the top of each user's preference list. However in the p-PGCP, the popularity of the channels among all users is also taken into account in such a way that a channel which is popular among more users is assigned a higher priority of pre-fetching. Simulation results demonstrate the fact that the proposed two algorithms sufficiently take advantage of users' behavior patterns and is capable of reducing the channel switching time compared with existing approaches.

Individual alerting efficiency modulates time perception.

Time perception plays a fundamental role in human perceptual and motor activities, and can be influenced by various factors, such as selective attention and arousal. However, little is known about the influence of individual alerting efficiency on perceived duration. In this study, we explored this question by running two experiments. The Attentional Networks Test was used to evaluate individual differences in alerting efficiency in each experiment. Temporal bisection (Experiment 1) and time generalization task (Experiment 2) were used to explore the participants’ perception of duration. The results indicated that subjects in the high alerting efficiency group overestimated interval durations and estimated durations more accurately compared with subjects in the low alerting efficiency group. The two experiments showed that the sensitivity of time was not influenced by individual alerting efficiency. Based on previous studies and current findings, we infer that individual differences in alerting efficiency may influence time perception through modulating the latency of the attention-controlled switch and the speed of the peacemaker within the framework of the internal clock model.

Simultaneously Reducing Latency and Power Consumption in OpenFlow Switches

The Ethernet switch is a primary building block for today's enterprise networks and data centers. As network technologies converge upon a single Ethernet fabric, there is ongoing pressure to improve the performance and efficiency of the switch while maintaining flexibility and a rich set of packet processing features. The OpenFlow architecture aims to provide flexibility and programmable packet processing to meet these converging needs. Of the many ways to create an OpenFlow switch, a popular choice is to make heavy use of ternary content addressable memories (TCAMs). Unfortunately, TCAMs can consume a considerable amount of power and, when used to match flows in an OpenFlow switch, put a bound on switch latency. In this paper, we propose enhancing an OpenFlow Ethernet switch with per-port packet prediction circuitry in order to simultaneously reduce latency and power consumption without sacrificing rich policy-based forwarding enabled by the OpenFlow architecture. Packet prediction exploits the temporal locality in network communications to predict the flow classification of incoming packets. When predictions are correct, latency can be reduced, and significant power savings can be achieved from bypassing the full lookup process. Simulation studies using actual network traces indicate that correct prediction rates of 97% are achievable using only a small amount of prediction circuitry per port. These studies also show that prediction circuitry can help reduce the power consumed by a lookup process that includes a TCAM by 92% and simultaneously reduce the latency of a cut-through switch by 66%.

Linux PREEMPT-RT v2.6.33 versus v3.6.6

Linux was originally designed as a general purpose operating system without consideration for real-time applications. Recently, it became a more reliable candidate in the real-time field due to its daily improvements, both for general purpose and real-time usages. In this research, we test two Linux PREEMPT-RT versions (v3.6.6 and v2.6.33.7) in the aim of benchmarking its performance and behaviour to give an insight whether the enhancements in its kernel are improving the determinism of the operating system. Our benchmark will be based on the following experimental measurements' metrics: thread switch latency, interrupt latency, sustained interrupt frequency, mutex and semaphore acquisition and release durations, and finally the locking behaviour of mutex. These measurements are executed for each Linux version, on the same x86 platform (ATOM processor) using the same test framework and measurement equipment. Comparing the results show that Linux v3.6.6 has significantly better worst case results which makes the actual Linux PREEMPT-RT version a better candidate for RT-applications. Suggestions are made for further improvements.

Opportunistic medium access control for maximizing packet delivery rate in dynamic access networks

One of the key challenges to enabling efficient cognitive radio (CR) communications is how to perform opportunistic medium access control (MAC) that maximizes spectrum efficiency. Several CRN MAC protocols have been designed assuming relatively static primary radio (PR) channels with average idle durations largely exceed CR transmission times. For such CR environment, typical multichannel MAC protocols, which select the best quality channel, perform reasonably well. However, when such mechanism is employed in a CRN that coexists with highly dynamic licensed PR networks (PRNs), where PR channel idle durations are comparable to CR transmission times, the forced-termination rate for CR transmission can significantly increase, leading to a reduction in network throughput. To reduce the forced-termination rate, many MAC protocols have been proposed to account for the dynamic time-varying nature of PR channels by requiring communicating CR users to consistently perform channel switching according to PR activities. However, such channel-switching strategy introduces significant overhead and latency, which negatively affect network throughput. Hence, in this paper, we propose a probabilistic channel quality- and availability-aware CRN MAC. Our protocol uses a novel channel assignment mechanism that attempts at maximizing the packet success probability of each transmission and hence avoids the significant overhead and latency of channel switching. Simulation results show that by being quality- and availability-aware, our protocol provides better spectrum utilization by decreasing the forced-termination rate and improving network throughput.

Spectrum-Aware Mobility Management in Cognitive Radio Cellular Networks

Cognitive radio (CR) networks have been proposed as a solution to both spectrum inefficiency and spectrum scarcity problems. However, they face several challenges based on the fluctuating nature of the available spectrum, making it more difficult to support seamless communications, especially in CR cellular networks. In this paper, a spectrum-aware mobility management scheme is proposed for CR cellular networks. First, a novel network architecture is introduced to mitigate heterogeneous spectrum availability. Based on this architecture, a unified mobility management framework is developed to support diverse mobility events in CR networks, which consists of spectrum mobility management, user mobility management, and intercell resource allocation. The spectrum mobility management scheme determines a target cell and spectrum band for CR users adaptively dependent on time-varying spectrum opportunities, leading to increase in cell capacity. In the user mobility management scheme, a mobile user selects a proper handoff mechanism so as to minimize a switching latency at the cell boundary by considering spatially heterogeneous spectrum availability. Intercell resource allocation helps to improve the performance of both mobility management schemes by efficiently sharing spectrum resources with multiple cells. Simulation results show that the proposed method can achieve better performance than conventional handoff schemes in terms of both cell capacity as well as mobility support in communications.

Removing path-switching cost in video delivery over multiple paths in mobile networks

The pace at which powerful portable wireless consumer devices such as smartphones and tablets have been adopted has not been matched by the ability of mobile networks to deliver high-quality video streams consistently to such nomadic users. In this work, we propose CMT-NEMO, a novel concurrent multipath transfer scheme for the delivery of scalable video content to users in multihomed mobile networks such as those expected to be found in public transport scenarios. Recent research in this context has shown that the single largest limiting factor for perceived video quality is the overhead introduced by path switching operations in multihomed mobile networks. CMT-NEMO eliminates the need for path switching and, by removing the associated path switching latency, provides a substantial performance improvement across a wide range of bandwidths and test sequences. An average Y-PSNR improvement of 5.9 dB is achieved when compared with previously proposed schemes.

State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores

In this work, we investigate state-retentive power gating of register files for leakage reduction in multicore processors supporting multithreading. In an in-order core, when a thread gets blocked due to a memory stall, the corresponding register file can be placed in a low leakage state through power gating for leakage reduction. When the memory stall gets resolved, the register file is activated for being accessed again. Since the contents of the register file are not lost and restored on wakeup, this is referred to as state-retentive power gating of register files. While state-retentive power gating in single cores has been studied in the literature, it is being investigated for multicore architectures for the first time in this work. We propose specific techniques to implement state-retentive power gating for three different multicore processor configurations based on the multithreading model: 1) coarse-grained multithreading, 2) fine-grained multithreading, and 3) simultaneous multithreading. The proposed techniques can be implemented as design extensions within the control units of the in-order cores. Each technique uses two different modes of leakage states: low-leakage savings and low wake-up and high-leakage savings and high wake-up latency. The overhead due to wake-up latency is completely avoided in two techniques while it is hidden for most part in the third approach, either by overlapping the wake-up process with the thread context switching latency or by executing instructions from other threads ready for execution. The proposed techniques were evaluated through simulations with multiprogrammed workloads comprised of SPEC 2000 integer benchmarks. Experimental results show that in an 8-core processor executing 64 threads, the average leakage savings were 42 percent in coarse-grained multithreading, while they were between seven percent and eight percent for finegrained and simultaneous multithreading.

A low-latency modular switch for CMP systems

As technology advances, the number of cores in Chip MultiProcessor systems and MultiProcessor Systems-on-Chips keeps increasing. The network must provide sustained throughput and ultra-low latencies. In this paper we propose new pipelined switch designs focused in reducing the switch latency. We identify the switch components that limit the switch frequency: the arbiter. Then, we simplify the arbiter logic by using multiple smaller arbiters, but increasing greatly the switch area. To solve this problem, a second design is presented where the routing traversal and arbitrations tasks are mixed. Results demonstrate a switch latency reduction ranging from 10% to 21%. Network latency is reduced in a range from 11% to 15%.

An upstream multi-wavelength shared PON based on tunable self-seeding Fabry-Pérot laser diode for upstream capacity upgrade and wavelength multiplexing

We proposed an Upstream Multi-Wavelength Shared (UMWS) PON architecture based on a tunable self-seeding Fabry-Perot laser diode (FP-LD) at ONU. The performances of the wavelength and power stability, side-mode suppression ratio (SMSR), tuning range for the proposed tunable self-seeding laser module at ONU are experimentally investigated. The BER is measured with direct modulation on FP-LD of 1.25 Gbps upstream data. The extensive simulations not only evaluate the enhanced performance from the upstream wavelength-sharing, but also for the first time investigate the impact of channel Switch Latency (SL) on the network performance.

Reducing channel change delay in IPTV by predictive pre-joining of TV channels

One of the major concerns of IPTV network deployment is channel change delay (also known as zapping delay). This delay can add up to 2 s or more, and its main culprits are synchronisation and buffering of the media streams. Proving the importance of the problem is the already significant amount of literature addressing it. We start this paper with a survey of techniques proposed to reduce IPTV channel change delay. Then, by analysing an extensive dataset from an operational IPTV provider – comprising 255 thousand users, 150 TV channels, and covering a 6-month period – we have observed that most channel switching events are relatively predictable: users very frequently switch linearly, up or down to the next TV channel. This fact motivated us to use this dataset to analyse in detail a specific type of solutions to this problem, namely, predictive pre-joining of TV channels. In these schemes each set top box (STB) simultaneously joins additional multicast groups (TV channels) along with the one that is requested by the user. If the user switches to any of these channels the switching latency is virtually eliminated, not affecting therefore user's experience. We start by evaluating a simple scheme, where the neighbouring channels (i.e., channels adjacent to the requested one) are pre-joined by the STB during zapping periods. Notwithstanding the simplicity of this scheme, trace-driven simulations show that the zapping delay can be virtually eliminated for a significant percentage of channel switching requests. For example, when sending the previous and the next channel concurrently with the requested one, for only 1 min after a zapping event, switching delay is eliminated for close to half of all channel switching requests. Importantly, this result is achieved with a negligible increase of bandwidth utilisation in the access link. Other more complex schemes where user behaviour is tracked were also evaluated, but the improvement over the simple scheme was insignificant.

Analysis of IPACT network performance considering channel switch latency for WDM-EPON

In wavelength-division multiplexing (WDM) ethernet passive optical networks (EPONs), to realize the statistical multiplexing of upstream wavelength resources, some optical tunable components are introduced in the optical network units. However, the switch latency (SL) of these tunable components constrains the performance of WDM-EPON. In this letter, we extend the mathematical model of the WDM interleaved polling with adaptive cycle time (IPACT) scheme by additionally considering the SL conditions. We also investigate the effect of channel SL on network performance. The simulation results show that the performance of WDM-IPACT-SL deteriorates as the SL increases.

Time estimation of fear cues in human observers

Previous research suggests that time judgments are a function of the affective properties of to-be-timed stimuli and that time judgments are longer for stimuli that are fear-inducing (e.g., Hare, 1963; Watts and Sharrock, 1984). The goals of the present study were twofold: to replicate the effect of a fear cue on time estimation, and to evaluate the mechanism underlying the effect. Seven stimulus durations in two different duration ranges (short: 250-1000 ms; long: 400-1600 ms) were employed in the bisection procedure. Adult human participants were exposed to two successive sessions, one each with the short and long range. Images from the International Affective Picture System (IAPS; Lang et al., 2008) that were rated on three scales including arousal and fear were presented as temporal stimuli. Three images that were rated high on fear and three rated low served as fear cues and neutral control images, respectively. Results indicated that for both ranges, judgments were longer for fear cues than for neutral images, and that the magnitude of the effect did not differ between ranges as measured by the bisection point. Application of scalar expectancy theory (SET; Gibbon, 1977; Church, 1984) to these results suggests that the fear effects were mediated by switch latency of an internal clock, rather than by clock speed.

Photonic Combinatorial Network for Contention Management in 160 Gb/s-Interconnection Networks Based on All-Optical 2$\,\times\,$2 Switching Elements

A modular photonic interconnection network based on a combination of basic 2times2 all-optical nodes including a photonic combinatorial network for the packet contention management is presented. The proposed architecture is synchronous, can handle optical time division multiplexed (OTDM) packets up to 160 Gb/s, exhibits self-routing capability, and very low switching latency. In such a scenario, OTDM has to be preferred to wavelength division multiplexing (WDM) because in the former case, the instantaneous packet power carries the information related to only one bit, making the signal processing based on instantaneous nonlinear interactions between packets and control signals more efficient. Moreover, OTDM can be used in interconnection networks without caring about the propagation impairments because of the very short length (<100 m) of the links in these networks. For such short-range networks, the packet synchronization can be solved at the network boundary in the electronic domain without the need of complex optical synchronizers. In this paper, we focus on a photonic combinatorial network able to detect the contentions, and to optically drive the contention resolution block and the switching control block. The implementation of the photonic combinatorial network is based on semiconductor devices, which makes the solution very promising in terms of compactness, stability, and power consumption. This implementation represents the first example of complex photonic combinatorial network for ultrafast digital processing. The network performance has been investigated for bit streams at 10 Gb/s in terms of bit error rate (BER) and contrast ratio. Moreover, the suitability of the 2times2 photonic node architecture exploiting the earlier mentioned combinatorial network has been verified at a bit rate up to 160 Gb/s. In this way, the potential of photonic digital processing for the next generation broad band and flexible interconnection networks has been demonstrated.