Switch Hardware Research Articles

Energy-Efficient and Load-Proportional eNodeB for 5G User-Centric Networks: A Multilevel Sleep Strategy Mechanism

Today, dense network deployment is being considered as one of the effective strategies to meet the capacity and connectivity demands of the fifth-generation (5G) cellular system. Among several challenges, energy consumption will be a critical consideration in the 5G era. In this direction, base station (BS) on/off operation (sleep mode) is an effective technique for mitigating the excessive energy consumption in ultradense cellular networks. However, the current implementation of this technique is unsuitable for dynamic networks with fluctuating traffic profiles because of coverage constraints, quality-of-service (QoS) requirements, and hardware switching latency. To address this, we propose an energy/load proportional approach for 5G BSs with control/data plane separation. The proposed approach depends on a multistep sleep mode profiling and predicts the BS vacation time in advance. Such a prediction enables selecting the best sleep mode strategy while minimizing the effect of BS activation/reactivation latency, resulting in significant energy savings.

ZeroSDN: A Highly Flexible and Modular Architecture for Full-Range Distribution of Event-Based Network Control

Recent years have seen an evolution of software-defined networking (SDN) control plane architectures, starting from simple monolithic controllers, over modular monolithic controllers, to distributed controllers. We observe, however, that today's distributed controllers still exhibit inflexibility with respect to the distribution of control logic. Therefore, we propose a novel architecture of a distributed SDN controller, providing maximum flexibility with respect to distribution and improved manageability. Our architecture splits control logic into lightweight control modules, called controllets, based on a micro-kernel approach, reducing common controllet functionality to a bare minimum and factoring out all higher-level functionality. Lightweight controllets also allow for pushing control logic onto switches and enable local processing of data plane events to minimize control latency and communication overhead while leveraging SDN's global view to maximize control decision quality. Controllets are interconnected through a message bus supporting the publish/subscribe communication paradigm with specific extensions for content-based message filtering. Publish/subscribe allows for complete decoupling of controllets to further facilitate control plane distribution. Furthermore, we identify crucial requirements for practical on-switch deployments, where we employ lightweight virtualization techniques to ensure a safe control plane operation. We evaluate both, the scalability and performance properties of our architecture, including its deployment on a white-box networking hardware switch.

Priority-Based Flow Control for Dynamic and Reliable Flow Management in SDN

Software-defined networking (SDN) is a promising paradigm of computer networks, offering a programmable and centralized network architecture. However, although such a technology supports the ability to dynamically handle network traffic based on real-time and flexible traffic control, SDN-based networks can be vulnerable to dynamic change of flow control rules, which causes transmission disruption and packet loss in SDN hardware switches. This problem can be critical because the interruption and packet loss in SDN switches can bring additional performance degradation for SDN-controlled traffic flows in the data plane. In this paper, we propose a novel robust flow control mechanism referred to as priority-based flow control (PFC) for dynamic but disruption-free flow management when it is necessary to change flow control rules on the fly. PFC minimizes the complexity of flow modification process in SDN switches by temporarily adapting the priority of flow rules in order to substantially reduce the time spent on control-plane processing during run-time. Measurement results show that PFC is able to successfully prevent transmission disruption and packet loss events caused by traffic path changes, thus offering dynamic and lossless traffic control for SDN switches.

Enabling High Availability Service with oVirt Virtualization and CephFS

The online computing environment at STAR has generated demand for high availability of services (HAS) and a resilient uptime guarantee. Such services include databases, webservers, and storage systems that user and sub-systems tend to rely on for their critical workflows. Standard deployment of services on bare metal creates a problem if the fundamental hardware fails or loses connectivity. Additionally, the configuration of redundant failover nodes (a secondary Web service for example) requires constant syncing of configuration and content and sometimes manual interaction for switching hardware (DNS name comes to mind). For this project, we will focus on two tools: oVirt and Ceph. oVirt is an OpenSource virtualization management application that enables central management of hardware nodes, storage, and network resources used to deploy and monitor virtual machines. oVirt supports the deployment of a virtual environment for your data center leveraging automatic provisioning, live migration, and the ability to easily scale the number of hypervisors. oVirt enables the use of multiple storage technologies where you can store virtual machines, images, and templates within one or multiple storage systems. STAR’s recent efforts focused on deploying a CephFS POSIX compliant distributed storage system, we would enable the ability to couple our Ceph storage with the oVirt virtualization management system. When designing an intricate system for hosting critical services, it is a requirement to circumvent single points of failure. This work will involve the testing and viability of such an approach along with test cases for high availability, live migration, and service on demand.

Modelling Software-Defined Networking: Software and hardware switches

In Software-Defined Networking (SDN), a switch is a forwarding device that moves data packets in a network. A software switch handles forwarding functions in software and thus cannot forward packet at line speed while a hardware switch leverages optimised forwarding hardware to forward packets at line speed. However, there has been very little research in the literature to help network engineers understand the tradeoffs in choosing one over the other. In this paper, we develop a unified queueing model for characterizing the performance of hardware switches and software switches in SDN. The unified queueing model is an analytical tool for engineers to predict delay, packet loss and throughput in their SDN deployments. Existing queueing models of SDN have focused on performance analysis of software switches, while our work presented herein is the first to present a unified analysis of hardware and software switches. Our proposed models exhibit errors below 5% compared to simulation. Between a hardware and software switch, the evaluation shows that a hardware switch achieves an average 80% lower delay and up to 100% lower packet loss probability compared to a software switch. The more a hardware switch involves the controller for decisioning, the lower the gains in terms of packet delays through the switch.

PreFix

In modern datacenter networks (DCNs), failures of network devices are the norm rather than the exception, and many research efforts have focused on dealing with failures after they happen. In this paper, we take a different approach by predicting failures, thus the operators can intervene and "fix" the potential failures before they happen. Specifically, in our proposed system, named PreFix, we aim to determine during runtime whether a switch failure will happen in the near future. The prediction is based on the measurements of the current switch system status and historical switch hardware failure cases that have been carefully labelled by network operators. Our key observation is that failures of the same switch model share some common syslog patterns before failures occur, and we can apply machine learning methods to extract the common patterns for predicting switch failures. Our novel set of features (message template sequence, frequency, seasonality and surge) for machine learning can efficiently deal with the challenges of noises, sample imbalance, and computation overhead. We evaluated PreFix on a data set collected from 9397 switches (3 different switch models) deployed in more than 20 datacenters owned by a top global search engine in a 2-year period. PreFix achieved an average of 61.81% recall and 1.84x10 -5 false positive ratio, outperforming the other failure prediction methods for computers and ISP devices.

PreFix

In modern datacenter networks (DCNs), failures of network devices are the norm rather than the exception, and many research efforts have focused on dealing with failures after they happen. In this paper, we take a different approach by predicting failures, thus the operators can intervene and "fix" the potential failures before they happen. Specifically, in our proposed system, named PreFix, we aim to determine during runtime whether a switch failure will happen in the near future. The prediction is based on the measurements of the current switch system status and historical switch hardware failure cases that have been carefully labelled by network operators. Our key observation is that failures of the same switch model share some common syslog patterns before failures occur, and we can apply machine learning methods to extract the common patterns for predicting switch failures. Our novel set of features (message template sequence, frequency, seasonality and surge) for machine learning can efficiently deal with the challenges of noises, sample imbalance, and computation overhead. We evaluated PreFix on a data set collected from 9397 switches (3 different switch models) deployed in more than 20 datacenters owned by a top global search engine in a 2-year period. PreFix achieved an average of 61.81% recall and 1.84 * 10^-5 false positive ratio. It outperforms the other failure prediction methods for computers and ISP devices.

Encoding Short Ranges in TCAM Without Expansion: Efficient Algorithm and Applications

We present range encoding with no expansion (RENE)— a novel encoding scheme for short ranges on Ternary content addressable memory (TCAM), which, unlike previous solutions, does not impose row expansion , and uses bits proportionally to the maximal range length. We provide theoretical analysis to show that our encoding is the closest to the lower bound of number of bits used. In addition, we show several applications of our technique in the field of packet classification, and also, how the same technique could be used to efficiently solve other hard problems, such as the nearest-neighbor search problem and its variants. We show that using TCAM, one could solve such problems in much higher rates than previously suggested solutions, and outperform known lower bounds in traditional memory models. We show by experiments that the translation process of RENE on switch hardware induces only a negligible 2.5% latency overhead. Our nearest neighbor implementation on a TCAM device provides search rates that are up to four orders of magnitude higher than previous best prior-art solutions.

Multistage switching hardware and software implementations for student experiment purpose

Current communication and internet networks are underpinned by the switching technologies that interconnect one network to the others. Students’ understanding on networks rely on how they conver the theories. However, understanding theories without touching the reality may exert spots in the overall knowledge. This paper reports the progress of the multistage switching design and implementation for student laboratory activities. The hardware and software designs are based on three stages clos switching architecture with modular 2x2 switches, controlled by an arduino microcontroller. The designed modules can also be extended for batcher and bayan switch, and working on circuit and packet switching systems. The circuit analysis and simulation show that the blocking probability for each switch combinations can be obtained by generating random or patterned traffics. The mathematic model and simulation analysis shows 16.4% blocking probability differences as the traffic generation is uniform. The circuits design components and interfacing solution have been identified to allow next step implementation.

Dynamic, Fine-Grained Data Plane Monitoring With Monocle

Ensuring network reliability is important for satisfying service-level objectives. However, diagnosing network anomalies in a timely fashion is difficult due to the complex nature of network configurations. We present Monocle — a system that uncovers forwarding problems due to hardware or software failures in switches, by verifying that the data plane corresponds to the view that an SDN controller installs via the control plane. Monocle works by systematically probing the switch data plane; the probes are constructed by formulating the switch forwarding table logic as a Boolean satisfiability (SAT) problem. Our SAT formulation quickly generates probe packets targeting a particular rule considering both existing and new rules. Monocle can monitor not only static flow tables (as is currently typically the case), but also dynamic networks with frequent flow table changes. Our evaluation shows that Monocle is capable of fine-grained monitoring for the majority of rules, and it can identify a rule suddenly missing from the data plane or misbehaving in a matter of seconds. In fact, during our evaluation Monocle uncovered problems with two hardware switches that we were using in our evaluation. Finally, during network updates Monocle helps controllers cope with switches that exhibit transient inconsistencies between their control and data plane states.

PIAS: Practical Information-Agnostic Flow Scheduling for Commodity Data Centers

Many existing data center network (DCN) flow scheduling schemes, that minimize flow completion times (FCT) assume prior knowledge of flows and custom switch functions, making them superior in performance but hard to implement in practice. By contrast, we seek to minimize FCT with no prior knowledge and existing commodity switch hardware. To this end, we present PIAS, a DCN flow scheduling mechanism that aims to minimize FCT by mimicking shortest job first (SJF) on the premise that flow size is not known a priori . At its heart, PIAS leverages multiple priority queues available in existing commodity switches to implement a multiple level feedback queue, in which a PIAS flow is gradually demoted from higher-priority queues to lower-priority queues based on the number of bytes it has sent. As a result, short flows are likely to be finished in the first few high-priority queues and thus be prioritized over long flows in general, which enables PIAS to emulate SJF without knowing flow sizes beforehand. We have implemented a PIAS prototype and evaluated PIAS through both testbed experiments and ns-2 simulations. We show that PIAS is readily deployable with commodity switches and backward compatible with legacy TCP/IP stacks. Our evaluation results show that PIAS significantly outperforms existing information-agnostic schemes, for example, it reduces FCT by up to 50% compared to DCTCP [11] and L2DCT [32] ; and it only has a 1.1% performance gap to an ideal information-aware scheme, pFabric [13] , for short flows under a production DCN workload.

A cross-layer flow schedule with dynamical grouping for mitigating larger-scale TCP incast

Data center network (DCN), a type of network featuring low delays and high bandwidths, exchanges information rapidly through high-performance network switches. Currently, DCN provides various distributed services to satisfy user requirements. However, the size of buffers in the switches of DCNs is limited, thus causing throughput collapse when transmission control protocol (TCP) is used for multiple-to-one transmissions. Dropped packets result in additional retransmission costs and cause a substantial decrease in the efficient use of network bandwidths. Such a decrease in network performance is called a TCP incast problem. Previous studies have typically focused on modifying the original TCP or increasing additional switch hardware costs; rarely have studies focused on the existing DCN environments. Therefore, this study proposes using a cross-layer flow schedule with dynamical grouping (CLFS-DG) scheme to reduce the effect of TCP incast in DCNs. In CLSF-DG, data transmission schedules are organized by a receiver using application-level information. Multiple data flows are then grouped for simultaneously transmission to improve TCP throughput and satisfy deadline requirements. CLFS-DG can be applied to inexpensive switches without extra hardware support, substantially reducing hardware costs. The simulation result indicated that CLFS-DG can effectively prevent TCP incast occurrence and ensure the quality of service in both local networks and fat-tree topologies typically applied in the DCN. A realistic multiple-to-one transmission in the one-hop local network scenario had been set up and tested. The average error rate of the simulation results and actual experimental results is small and about 4.6%. The results show that CLFS-DG can actually be applied to real large networks.

A Database Approach to SDN Control Plane Design

Software-defined networking (SDN) is a well-known example of a research idea that has been reduced to practice in numerous settings. Network virtualization has been successfully developed commercially using SDN techniques. This paper describes our experience in developing production-ready, multi-vendor implementations of a complex network virtualization system. Having struggled with a traditional network protocol approach (based on OpenFlow) to achieving interoperability among vendors, we adopted a new approach. We focused first on defining the control information content and then used a generic database protocol to synchronize state between the elements. Within less than nine months of starting the design, we had achieved basic interoperability between our network virtualization controller and the hardware switches of six vendors. This was a qualitative improvement on our decidedly mixed experience using OpenFlow. We found a number of benefits to the database approach, such as speed of implementation, greater hardware diversity, the ability to abstract away implementation details of the hardware, clarified state consistency model, and extensibility of the overall system.

A TestBed for Deployment of Datacenter Switches for Training Purposes

Today’s network industry needs highly qualified engineers to understand, configure, develop and upgrade switches that can build scalable high performance and ultra-low latency networks. This paper describes a new networking laboratory that has been set up to provide hands-on experience on datacenter network switches, such as ARISTA, programming and monitoring the traffic. This paper explains the networking laboratory coursework that students carry out during the course of a semester. The laboratory consists of six hands on experiments on the latest datacenter switches from Arista Networks, two programming assignments that teaches some of the protocols used at data link layer and routing protocols used at the network layer of OSI reference model. The final two laboratory experiments use the Wireshark software tool for traffic monitoring and peeking into details of some of the protocols in TCP/IP such as ARP protocol, Ethernet and so forth. The coursework details include the switch basics, switch hardware, Extensible Operating System (EOS), configuration of Link Aggregation Control Protocol, Multi-chassis Link Aggregation Protocol, Access Control Lists, and Open Short Path First version 2 on Arista switches 7050T-64 and 7048T-4S. The programming tasks cover High-level Data Link Control (HDLC) and Routing Algorithms.

Survey of Photonic Switching Architectures and Technologies in Support of Spatially and Spectrally Flexible Optical Networking [Invited

As traffic volumes carried by optical networks continue to grow by tens of percent year over year, we are rapidly approaching the capacity limit of the conventional communication band within a single-mode fiber. New measures such as elastic optical networking, spectral extension to multi-bands, and spatial expansion to additional fiber overlays or new fiber types are all being considered as potential solutions, whether near term or far. In this tutorial paper, we survey the photonic switching hardware solutions in support of evolving optical networking solutions enabling capacity expansion based on the proposed approaches. We also suggest how reconfigurable add/drop multiplexing nodes will evolve under these scenarios and gauge their properties and relative cost scalings. We identify that the switching technologies continue to evolve and offer network operators the required flexibility in routing information channels in both the spectral and spatial domains. New wavelength-selective switch designs can now support greater resolution, increased functionality and packing density, as well as operation with multiple input and output ports. Various switching constraints can be applied, such as routing of complete spatial superchannels, in an effort to reduce the network cost and simplify the routing protocols and managed pathway count. However, such constraints also reduce the transport efficiency when the network is only partially loaded, and may incur fragmentation. System tradeoffs between switching granularity and implementation complexity and cost will have to be carefully considered for future high-capacity SDM–WDM optical networks. In this work, we present the first cost comparisons, to our knowledge, of the different approaches in an effort to quantify such tradeoffs.

Modelling and dimensioning of a high-radix datacentre optical packet switch with recirculating optical buffers

Recently, high port-count optical packet switches, based on the Arrayed Waveguide Grating (AWG) device, have been proposed for providing the very high bandwidth and connectivity degree that will be required in future datacentre interconnection networks. A practical, cost-effective realisation of such a switch requires that over-subscription of the AWG cross-connect output ports be allowed, with the resulting packet contention being resolved using a packet buffering facility in the switch. In this paper, we propose an efficient AWG switch architecture of this type that uses a recirculating optical packet buffering scheme and we develop analytic modelling methods to estimate the switch packet blocking probability and packet buffering delay. The analytic model resolves internal traffic flows in the switch as Markov-modulated Poisson Processes (MMPP) and also allows modelling of offered load to the switch as a MMPP process. Taking this model of the switch, we first show its accuracy compared to discrete event simulations and then use it to develop a heuristic optimisation algorithm to dimension the switch hardware components, with the objective of minimising the operating cost by optimally dimensioning the main power consuming components, subject to constraints on the maximum contention probability and average and maximum propagation delays. The resulting optimised switch design demonstrates the proposed architecture to be a promising candidate for future high-port count datacentre switches.

Efficient mismatched packet buffer management with packet order-preserving for OpenFlow networks

OpenFlow-based networks simplify network management and improve network programmability by centralized network control. Existing OpenFlow networks employ packet-granularity mismatched packet buffer management to reduce the switch-controller communication overhead. However, the impact of packet buffer management granularity on network performance has not been well investigated yet. In this paper, we propose a novel design of flow-granularity mismatched packet buffer management model for OpenFlow networks, which outperforms the existing packet-granularity buffer management approaches with less communication overhead between switches and controllers. By designing the flow action pre-processing mechanism, we prevent per-flow packet disorder with less packet drop ratio. We evaluate the performance of the proposed flow-granularity mismatched packet buffer management scheme by building prototypes on both software and hardware switches. Experimental results reveal that our proposed method can effectively reduce the switches-controllers communication overhead, as well as preserve packet order for multi-flow OpenFlow networks.

Fine‐grained hardware switching scheme for power reduction in multiplication

This Letter presents a fine-grained hardware switching scheme to choose from the proper hardware for low power computing. It exploits the word-length optimisation opportunities for multiplication unit. With the proposed technique, the gate-level simulation result on OpenRISC shows 23.7% power reduction for the multiplication unit, which accounts for 9.5% power reduction for its execution unit.

Reconfigurable Farrow Structure-Based FRM Filters for Wireless Communication Systems

Recent trends in mobile technology are toward supporting multi-standard communication systems on the same device. This requires their design to be based on some kind of reconfigurable techniques. Also, in cognitive applications, intelligent bandwidth allocation for efficient spectrum utilization requires altering the bandwidth within the same communication channel. Digital filters with non-uniform and varying bandwidths can be used to channelize different frequencies. Efficient designs of such filters are proposed in this paper. Frequency response masking (FRM)-based design is used, where the masking filters can be tuned to a desired set of frequencies by using a variable bandwidth (VBW) digital filter, configured as Farrow structure. For each of the chosen bandwidth, a corresponding masking filter response can be obtained, using the Farrow structure. A novel extension of FRM is proposed in this paper, using two approaches, to realize more than one sharp filter response from the same prototype linear-phase low-pass filter. In both approaches, the masking filters of the FRM filter are realized using Farrow structure. In the first approach, only a set of two Farrow structure filters are required to realize all the required channels. The channel selection is then carried out by varying a single parameter on each of the two masking filters. In the second approach, every channel is realized using a set of two Farrow structure filters and the channel is selected by means of hardware switching techniques. In addition to reconfigurability, hardware implementation complexity of Farrow structure-based VBW is lower compared to the direct FIR filter structure when designed for large set of bandwidths.

Software Design Principles to Enhance SDN Architecture

SDN as a network architecture emerged on top of existing technologies and knowledge. Through defining the controller as a software program, SDN made a strong connection between networking and software engineering. Traditionally, network programs were vendor specific and embedded in hardware switches and routers. SDN focuses on isolation between control and forwarding or data planes. However, in the complete SDN network, there are many other areas (i.e. CPU, memory, hardware, bandwidth and software). In this paper, we propose extending SDN architecture and propose isolation layers with the goal of improving the overall network design. Such flexible architecture can support future evolution and changes without the need to significantly change original components or modules.