Switching Glitches Research Articles

A Pseudo-Random Signal Generator for Offset Calibration Circuit

A pseudo-random signal generator based on 0.5μm CMOS technology is presented, and it is applied for an auto-zero operational amplifier. The generator circuit includes a linear feedback shift register for generating pseudo-random sequences, and a multi-level counter module for counting the system clock pulses. A group of pseudo-random codes generated by the linear feedback shift register are as the initial value of the counter. When the counter reaches the maximum value, the output of the counter will control the output signal to flip. At the same time, a new group of the pseudo-random code will reset the counter again, and finally generate a square wave signal whose frequency varies randomly. The generator circuit is simulated and verified. The simulation results show that the frequency of the output signal can vary from 2 kHz to 4 kHz with random characteristic. The generated pseudo-random signal can be used for the switching clock control of the auto-zero operational amplifier offset calibration circuit, so that the switching glitch of the auto-zero op-amp is random, which can significantly reduce the harmonics in the output signal of the op-amp.

A 10-GS/s NRZ/Mixing DAC With Switching-Glitch Compensation Achieving SFDR >64/50 dBc Over the First/Second Nyquist Zone

This article presents a high-linearity wide-bandwidth current-steering digital-to-analog converter (DAC). To overcome the code-dependent current-switching glitch effect, which seriously degrades the DAC linearity, a switching-glitch compensation (SGC) technique, which is realized with glitch duplicators, is proposed to generate a complementary amount of switching glitch at the DAC output. Hence, the amount of switching glitch at the DAC output becomes code-independent, thus improving the linearity of the DAC output. In addition, a decorrelator is proposed to randomize the mismatch effect of the glitch duplicators, thus eliminating the mismatch-induced spur at the DAC output spectrum. A 14-bit 10-GS/s non-return-to-zero (NRZ)/Mixing DAC with SGC is realized in 28-nm CMOS. Measurement results show that the spurious free-dynamic range (SFDR) is improved up to around 20 dB by the SGC. Therefore, this DAC with SGC achieves an SFDR >64 dBc over the entire first Nyquist zone and >50 dBc over the entire second Nyquist zone. Compared to prior state-of-the-art CMOS DACs with an output frequency <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(f_{\mathrm {out}}) \ge3.4$ </tex-math></inline-formula> GHz, this DAC with SGC achieves a 12.5-dB better SFDR with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\mathrm {out}}$ </tex-math></inline-formula> near 10 GHz and a 1.4x higher <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\mathrm {out}}$ </tex-math></inline-formula> with an SFDR larger than 50 dBc.

A Model Study of an Error-Free Magnetization Reversal Through Dipolar Coupling in a Two-Magnet System

A systematic study on the feasibility of an error-free switching of two nanomagnets coupled via their dipolar fields by applying a spin current to one of them is presented. It is demonstrated that the dynamic nature of dipolar interaction between the nanomagnets may cause the magnetization of the second magnet to precess back to its original state despite having crossed the free-axis equatorial plane during the transient phase. This non-reversal is very different than the purely successful or unsuccessful switchings noted in other reversal analyses presented in the literature and, in this paper, is referred to as a dipolar switching glitch. The dynamic dipolar coupling between nanomagnets creates temporary titled precessional trajectories pushing the magnetization of the nanomagnet into high-energy states. Relaxation from these high-energy positions leads to fast, but quasi-random switching behavior. The maximum separation between the magnets for perfect coupling has been quantified as a function of the magnet planar dimensions. It is also shown that the simpler models that do not consider the mutual coupling between the two magnets underestimate the maximum allowed separation between the two magnets and, as such, are too conservative.

Exploration of Low-Power High-SFDR Current-Steering D/A Converter Design Using Steep-Slope Heterojunction Tunnel FETs

Steep-slope heterojunction tunnel field-effect transistor (HTFET) devices promise new opportunities beyond CMOS in low-power high-performance communication applications. In this paper, the circuit design optimization of a low-power 14-bit 1-GS/s current-steering digital-to-analog converter (DAC) using 0.4/0.3 V mixed-supply HTFETs is explored. Based on the device characteristics comparison and circuit analysis, it is shown in this paper that HTFET endorses significant differences in both $I$ – $V$ and $C$ – $V$ due to the steep-slope tunneling mechanism and a nature of vertically fabricated structure. While such differences significantly affect the circuit design corners, this paper gives the device-circuit co-optimization for the HTFET DAC, reaching at higher current source output impedance, less nonlinear switching glitch distortions, and thus superior spectral performance over the Si-CMOS DAC. HTFET device variation is also discussed, and calibration techniques are adopted for the static matching accuracy.

A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ

A 14 bit 500 MS/s current-steering digital-to-analog converter (DAC) was designed and fabricated in 0.13 CMOS process. For traditional wide-band current-steering DACs, the spurious-free dynamic range (SFDR) is limited by nonlinear distortions from the code-dependent load variations and the code-dependent switching glitches. They are analyzed in this paper and mitigated by the proposed complementary switched current sources (CSCS) and time-relaxed interleaving digital- random-return-to-zero (TRI-DRRZ), respectively. The proposed techniques are fabricated and measured, with an SFDR of 84.8 dB at 11 MHz signal frequency and 73.5 dB at 244 MHz. The DAC consumes 299 mW from a mixed power supply of 1.2 V and 2.5 V with an active area of . Index Terms—Digital-to-analog converter (DAC), interleaving, return-to-zero (RZ), spurious-free dynamic range (SFDR).

A 14-bit 250-MS/s current-steering CMOS digital-to-analog converter

A 14-bit 250-MS/s current-steering digital-to-analog converter (DAC) was fabricated in a 0.13 μm CMOS process. In conventional high-speed current-steering DACs, the spurious-free dynamic range (SFDR) is limited by nonlinear distortions in the code-dependent switching glitches. In this paper, the bottleneck is mitigated by the time-relaxed interleaving digital-random-return-to-zero (TRI-DRRZ). Under 250-MS/s sampling rate, the measured SFDR is 86.2 dB at 5.5-MHz signal frequency and 77.8 dB up to 122 MHz. The DAC occupies an active area of 1.58 mm2 and consumes 226 mW from a mixed power supply of 1.2/2.5 V.

Impact of Switching Glitches in Class-G Power Amplifiers

Envelope elimination and restoration (EER) based transmitters have attracted attention recently for two reasons: 1) The desire for increased spectral efficiency has mandated modulation standards that have large peak-to-average ratios (PAR). The increase in spectral efficiency is traded off against a decrease in average power-added-efficiency (PAE) when a linear power amplifier is used; however, when EER is used, it is decoupled somewhat from spectral efficiency. 2) Through the use of fast on-chip signal processing, the natural advantage of scaled CMOS is exploited by enabling switching power amplifier classes (e.g., class-E). This letter examines limitations associated with voltage supply switching glitches in class-G power amplifiers.

The Switching Glitch Power Leakage Model

Power analysis attacks are based on analyzing the power consumption of the cryptographic devices while they perform the encryption operation. Correlation Power Analysis (CPA) attacks exploit the linear relation between the known power consumption and the predicted power consumption of cryptographic devices to recover keys. It has been one of the effective side channel attacks that threaten the security of CMOS circuits. However, few works consider the leakage of glitches at the logic gates. In this paper, we present a new power consumption model, namely Switching Glitch (SG) power leakage model, which not only considers the data dependent switching activities but also including glitch power consumptions in CMOS circuits. Additionally, from a theoretical point of view, we show how to estimate the glitch factor. The experiments against AES implementation validate the proposed model. Compared with CPA based on Hamming Distance model, the power traces of recovering keys have been decreased by as much as 28.9%.