Switching Energy Dissipation Research Articles

Mechanical Modulation of 2D Electronic Devices at Atto‐Joule Energy via Flexotronic Effect

AbstractIn addition to electrical, optical, and magnetic fields, mechanical forces have demonstrated a strong ability to modulate semiconductor devices. With the rapid development of piezotronics and flexotronics, force regulation has been widely used in field‐effect transistors (FETs), human–machine interfaces, light‐emitting diodes (LEDs), solar cells, etc. Here, a large mechanical modulation of electronic properties by nano‐Newton force in semiconductor materials with a large Young's modulus‐based force FET is reported. More importantly, this FET has ultralow switching energy dissipation (7 aJ per decuple current gain) and nearly zero leakage power; these values are even better than those of electronic FETs. This finding paves the way for practical applications of nanoforce modulation devices at high power efficiency.

Energy Efficient Configurable Layout of Logic Block in QCA Frame Work for an FPGA

Aims: Embedded system plays a vital role in today’s life. Hence, our interest is in areadelay- energy efficient embedded system design in post-CMOS technology, i.e., QCA. Objectives: The research is focused on efficient area-delay-energy Configurable Logic Block (CLB) design for Field-Programmable Gate Array architecture (FPGA) with successful simulation-based on next-generation technology, Quantum-dot cellular automata. Methods: Each proposed circuit is designed on post CMOS 4 dot 2 electron technology, i.e. QCA (Quantum dot Cellular Automata), is adopted in circuit implementation due to low power dissipation, high clock frequency and high package density. QCADesigner is used to verify the functionality of every circuit. QCAPro tool is used for determining power dissipation. Results: In contrast, a new approach of using de-multiplexer replacing the decoder has been introduced that results in the reduction of the average energy dissipation by almost 57%. A NOR based D flip-flop memory architecture and multiplexer are also used in the lookup table for the configurable logic block. The proposed architecture thus reduces the overall latency. The proposed CLB consists of 6356 QCA cells covering 7.44 um2 area. Write and read latency of proposed CLB are 12 and 7.25 QCA clock, respectively. Conclusion: The present paper concludes that read and write latency reduction occurs; average energy dissipation, leakage, and switching energy dissipation are reduced in a large amount resulting in an advantage of the overall minimization of the latency for the proposed CLB in the process.

Rotated majority gate-based 2n-bit full adder design in quantum-dot cellular automata nanotechnology

PurposeIn nano-scale-based very large scale integration technology, quantum-dot cellular automata (QCA) is considered as a strong and capable technology to replace the well-known complementary metal oxide semiconductor technology. In QCA technique, rotated majority gate (RMG) design is not explored greatly, and therefore, its advantages compared to original majority gate are unnoticed. This paper aims to provide a thorough observation at RMG gate with its capability to build robust circuits.Design/methodology/approachThis paper presents a new methodology for structuring reliable 2n-bit full adder (FA) circuit design in QCA utilizing RMG. Mathematical proof is provided for RMG gate structure. A new 1-bit FA circuit design is projected here, which is constructed with RMG gate and clock-zone-based crossover approach in its configuration.FindingsA new structure of a FA is projected in this paper. The proposed design uses only 50 number of QCA cells in its implementation with a latency of 3 clock zones. The proposed 1-bit FA design conception has been checked for its structure robustness by designing various 2, 4, 8, 16, 32 and 64-bit FA designs. The proposed FA designs save power from 46.87% to 25.55% at maximum energy dissipation of circuit level, 39.05% to 23.36% at average energy dissipation of circuit-level and 42.03% to 37.18% at average switching energy dissipation of circuit level.Originality/valueThis paper fulfills the gape of focused research for RMG with its detailed mathematical modeling analysis.

Switching energy dissipation pathway: in situ proton-induced transformation of AIE-active self-assemblies to boost photodynamic therapy.

With the morphological transformation of fluorescent self-assembled nanostructures, their functions can be varied simultaneously. However, little attention has been paid to the function variation in this process. Herein, we present aggregation-induced emission (AIE)-active self-assembled nanospheres to investigate the transformation-induced function variation by switching the energy dissipation pathway. The self-assembled nanospheres showed strong emission under neutral conditions, indicating that radiative decay dominates the energy dissipation. Under acidic conditions, the spheres transformed to vesicles and nanotubes, in which the excited energy was largely consumed by the intersystem crossing pathway and highly efficient reactive oxygen species (ROS) generation was afforded. In particular, this morphological transformation and function variation can smoothly proceed in acidic lysosomes, thus drastically boosting photodynamic cancer therapy.

Compact Modeling and Analysis of Voltage-Gated Spin-Orbit Torque Magnetic Tunnel Junction

Recently, experimental results have demonstrated that perpendicular magnetic tunnel junction (p-MTJ) with the antiferromagnetic(AFM)/ferromagnetic (FM)/oxide structure can achieve field-free spin-orbit torque (SOT) switching since the AFM metal strip can not only generate the SOT, but also provide an exchange bias (HEX), making it suitable for practical applications. However, owing to that the HEX is weak, such field-free SOT switching is incomplete, thus resulting in severe switching reliability. In addition, a large SOT switching current (ISOT) is also required, leading to high switching energy dissipation. In this paper, to address these issues, the voltage-controlled magnetic anisotropy (VCMA) is introduced to assist the SOT switching, and such novel switching method is referred as voltage-gated SOT (VGSOT). First, we develop a physics-based compact model for the three-terminal VGSOT-MTJ device, which includes three modules, i.e., the electrical module, the tunnel magnetoresistance module and the dynamic switching module. Then, the impact of the VCMA effect on the field-free SOT switching is investigated by solving a modified Landau-Lifshitz-Gilbert (LLG) equation with consideration of the VCMA, SOT and HEX. Simulation results show that thanks to the introduction of the VCMA effect, the critical ISOT can be reduced greatly, and the incomplete field-free SOT switching can be completed. With further analysis, we obtain a special switching condition, under which complete SOT field-free switching can be achieved with a shortest path and ultra-low power. Moreover, a novel write pulse scheme is proposed to achieve high speed and reliability.

Impact of Power Module Parasitic Capacitances on Medium-Voltage SiC MOSFETs Switching Transients

Increased switching speeds of wide bandgap (WBG) semiconductors result in a significant magnitude of the displacement currents through power module parasitic capacitances that are inherent in packaging design. This is of increasing concern, particularly in case of newly emerging medium-voltage (MV) SiC MOSFETs since the magnitude of the displacement currents can be several order higher due to the fast switching transients and increased voltage magnitudes of the SiC MOSFETs compared to their Si counter parts. The severity intensifies when the magnitude of the displacement current becomes comparable to a significant fraction of SiC MOSFETs rated current, leading to the worsened impact on the converter electromagnetic interference (EMI) as well as performance in terms of switching losses. The key objective of this article is to provide a detail insight into the impact of the module parasitic capacitances on the SiC MOSFET switching dynamics and losses. To realize this, a well-defined approach to dissect the switching energy dissipation is proposed, based on which the detailed analysis and quantitative measurements of the module parasitic capacitance impact on terms of added switching energy losses, and common-mode currents are investigated using a custom-packaged 10-kV half-bridge SiC MOSFET power modules. The theoretical analysis and experimental results obtained from dynamic as well as static characterization reveal that the impact of the module parasitic capacitance on the switching energy dissipation is twofold and substantially adverse such that it cannot be overlooked considering its intended application in the high-power MV power electronic converters.

Energy Efficient Novel Design of Static Random Access Memory Memory Cell in Quantum-dot Cellular Automata Approach

This paper introduces a peculiar approach of designing Static Random Access Memory (SRAM) memory cell in Quantum-dot Cellular Automata (QCA) technique. The proposed design consists of one 3-input MG, one 5-input MG in addition to a (2×1) Multiplexer block utilizing the loop-based approach. The simulation results reveals the excellence of the proposed design. The proposed SRAM cell achieves 16% and 15% improvement in terms of total number of Cell counts and Area. Similarly, the proposed design structure realizes the overall power dissipation savings up to 35.3% at maximum energy dissipation of circuit, 38.6% at average energy dissipation of circuit, 36.1% at minimum energy dissipation of circuit, 36.4% at average energy dissipation of circuit and 40.1% at average switching energy dissipation compared to the latest reported designs. The power analysis and structural analysis of the proposed design is compared with its state-of-the-art counterpart designs, using QCAPro and QCADesigner 2.0.3 tools. The proposed QCA based SRAM cell design can be taken as a base design in building an ultra-low power information generating systems like Microprocessors.

A novel robust exclusive-OR function implementation in QCA nanotechnology with energy dissipation analysis

Numerous scientific and fundamental hindrances have resulted in a slow down of silicon technology and opened new possibilities for emerging research devices and structures. The need has arisen to expedite new methods to interface these nanostructures for computing applications. Quantum-dot Cellular Automata (QCA) is one of such computing paradigm and means of encoding binary information. QCA computing offers potential advantages of ultra-low power dissipation, improved speed and highly density structures. This paper presents a novel two-input Exclusive-OR (XOR) gate implementation in quantum-dot cellular automata nanotechnology with minimum area and power dissipation as compared to previous designs. The proposed novel QCA based XOR structure uses only 28 QCA cells with an area of $$0.02\,\upmu \hbox {m}^{2}$$0.02μm2 and latency of 0.75 clock cycles. Also the proposed novel XOR gate is implemented in single layer without using any coplanar and multi-layer cross-over wiring facilitating highly robust and dense QCA circuit implementations. To investigate the efficacy of our proposed design in complex array of QCA structures, 4, 8, 16 and 32-bit even parity generator circuits were implemented. The proposed 4-bit even parity design occupies 9 and 50 % less area and has 12.5 and 22.22 % less latency as compared to previous designs. The 32-bit even parity design occupies 22 % less area than the best reported previous design. The proposed novel XOR structure has 28 % less switching energy dissipation, 10 % less average leakage energy dissipation and 19 % less average energy dissipation than best reported design. The simulation results verified that the proposed design offers significant improvements in terms of area, latency, energy dissipation and structural implementation requirements. All designs have been functionally verified in the QCADesigner tool for GaAs/AlGaAs heterostructure based semiconductor implementations. The energy dissipation results have been computed using an accurate QCAPro tool.

A Novel Low-Power Logic Circuit Design Scheme

This brief proposes a novel low-power digital logic design scheme based on the energy exchange in the switched inductor-capacitor (SLC) circuit. It presents a design paradigm which in ideal case may lead to a circuit capable of performing logic operations with no switching losses. In traditional integrated circuit design, the energy is stored in the output load capacitor through a pull-up path (corresponding to storing a logic 1). When the output changes its logic value, this stored energy is dissipated through the pull down path to the ground. In order to reduce this switching energy dissipation each time the load capacitor is discharged, we store its energy in the magnetic field of the inductor in the proposed SLC architecture. Whenever the output load needs to be charged again, we transfer the energy back from the inductor to the load capacitor. This significantly reduces the switching energy. We illustrated the operation of the SLC architecture through SPICE simulation. A brief discussion of some practical considerations for this architecture is also presented