Switching Activity Factor Research Articles

Energy management of fault-tolerant real-time embedded systems through switching-activity-based techniques

Energy management and fault tolerance are essential aspects in designing most real-time embedded systems, and dynamic voltage and frequency scaling (DVFS) is a fundamental approach in energy management. Using DVFS can lead to a considerable decrease in the system's reliability as the rate of transient faults increases due to low voltage and frequency. This study focuses on finding and implementing methods that address the following three issues in hard real-time embedded systems: energy consumption, fault tolerance, and time limitations. Switching activity depends on the nature of tasks. Since the switching activity is task-specific, the energy consumption of a task can be significantly greater than that of other tasks. As far as we know, previous studies on the power management of fault-tolerant real-time systems have not considered switching activity, so the impact of this factor is considered in this study. Multiple heuristic methods are proposed based on the switching activity factor to minimize energy consumption while sustaining the system's original reliability. In the proposed methods, the order of task execution is determined based on task switching activities. The methods are developed for both periodic and frame-based task models. The results show that the proposed methods can decrease the energy consumption by 12.7 %∼35.5 % for the periodic task model and 17.4 %∼45.2 % for the frame-based task model while preserving the system's reliability.

Asymptotically Linear Analysis and Gate Probability Allocation Schemes in Probabilistic Circuits

As the feature size of CMOS technology rapidly shrinks into the very deep submicrometer, the power density is getting higher and the circuit's reliability is seriously impacted by thermal noise. In order to reduce power dissipation, decreasing the supply voltage is a promising way. However, soft errors and decreased supply voltage make circuits behave probabilistic. Fortunately, some applications can tolerate a certain level of operation errors. The tradeoff between energy and reliability provides an opportunity to save the power consumption in the circuit. An asymptotically linear analysis (ALA) strategy is proposed to model the reliability evaluation of combinational logic circuits. Under the assumption that the gate error probability is not more than 0.05, an asymptotic linear matrix A is constructed by using the first-order term of the output error probability. When propagating the gate error probability from the input to the output ports, the ALA strategy only requires one multiplication between the matrix A and the gate error probability vector. There are significant differences in the complexity of computation of the ALA scheme and the Bayesian network (BN) and the probability transfer matrix (PTM) schemes, while its relative error (RE) is no more than 0.08 on the benchmark of LGSynth91. Furthermore, three schemes are proposed to adjust the gate error probability to meet the constraint on the error probability of the probabilistic CMOS (PCMOS) circuit's outputs. The proposed schemes can be performed to search the gate error probability combinations in the logic and circuit design stage of VLSI. During the power optimization, the switching activity factor in the asymptotically linear region is approximately invariant. It makes the power optimal model convex. The energy-saving ratio of the proposed power optimization scheme is 5%-6% higher than the existing schemes. The time consumption of the proposed three schemes is one-thousandth of the time consumed by the BN and PTM schemes. All the three schemes are verified by conducting experiments on the ISCAS'85 and IWLS'15 benchmark circuits. The simulation results establish the feasibility of the ALA and the performance of the proposed schemes.

POWER REDUCTION TECHNIQUE USING MULTIPLE SUPPLY VOLTAGE AND SWITCHING ACTIVITY ANALYSIS

Recent demand for low power VLSI circuits has been pushing the development of innovative approaches to reduce power dissipation. Supply voltage (V CC ) and switching activity factor (α) are main sources of dynamic power dissipation in CMOS technology. Furthermore, the power dissipation increases exponentially by the value of supply voltage. New approach based on switching activity analysis and multiple supply voltage is implemented successfully in logical circuits, taking in mind the critical path(s) of the design and switching activity factor of each element in the design. High supply voltage is applied on elements on the critical path(s). Elements off the critical path(s) are classified into categories according to their switching activity factors. The total power dissipation is reduced, while the propagation delay remains without any increase. The proposed approach combines the concepts of critical/non-critical paths and switching activity analysis to assign different V CCs to different elements.

Designing Method of Compact n-to-2n Decoders

What decoder is, everyone knows. The paper presents fast and efficient method of layouts design of n-to- 2n-lines decoders. Two scenarios of layout arrangement are proposed and described. Based on a few building blocks only, especially prepared, and appropriate procedure of their placement, a decoder of any size can be build. Layouts of all needed fundamental blocks were designed in CMOS technology, as standard library. Moreover, some important parameters, such area, power dissipation and delay, were assessed and compared for decoders designed with proposed method and traditional. Power consumption were considered under extended model, which takes into account changes of input vectors, not only switching activity factor. All designs were done in UMC 180 CMOS technology.

Low power design of a field sequential color LCoS chip

The low power design of a field sequential color (FSC) liquid crystal on silicon (LCoS) chip for near-to-eye application is presented in this paper. Dual power supplies are used in the design, that is, the supply for part of driving circuits is 3.3 V, and the one for the active matrix is 5.0 V. Serial-to-parallel conversion circuits are adopted to lower the pixel clock frequency of the chip. Also, an idle state is inserted into the pixel clock signal to decrease the switching activity factor to further reduce the power consumption. The LCoS chip is fabricated with 0.35 µm CMOS process and its power consumption is only about 300 mW.

Thermal distribution calculations for block level placement in embedded systems

Reliability is a very important concern for the embedded systems. Thermal distribution has become an important reliability concern for today’s integrated circuits and these circuits are being used increasingly in embedded systems. In traditional design flows, the temperature of the chip is assumed to be uniform across the substrate. However, non-uniform thermal distribution can be a major source of inaccuracy in delay and clock skew computations, and can have an impact on elctromigration reliability and self-heating effects for today’s very deep submicron technology. Hence, it has become necessary to obtain design with uniform temperature distribution to ensure minimum temperature gradient and avoid hot spots across the chip area. This will minimise reliability problems during the operation of the chip. The uniform temperature distribution can be achieved by appropriate placement of circuit blocks during the physical design. In this paper, thermal distribution of single chip embedded system on silicon is discussed. The thermal distribution calculations require evaluation of switching activity factor of circuit blocks. This factor is determined by computing activities of the blocks based on the application software of embedded system.