Switched-capacitor Power Converter Research Articles

A General Analysis of Resonant Switched-Capacitor Converters Using Peak Energy Storage and Switch Stress Including Ripple

This work presents a general analytical framework enabling large-signal characterization of resonant switched-capacitor (ReSC) power converters that accounts for passive component voltage and current ripple, for operation at and above resonance. From this, appropriate phase durations for minimized rms currents are derived, in addition to expressions for total passive component volume using an intuitive peak energy method. An example hardware prototype validates both the derived waveforms and timings—as well as total passive volume—through three comparable hardware configurations, one of which minimizes passive component volume. In addition, the proposed technique formulates analytical expressions for both rms currents and peak blocking voltages, facilitating refined loss estimation and component selection. Subsequent calculation of the large-signal Volt–Amp (VA) switch stress metric allows a more accurately quantified trade-off between active and passive components compared to prior work, which has not fully accounted for ripple. Four common ReSC topologies are exemplified throughout, with topology specific parameters documented for reference.

A Design Methodology for High-Voltage, Highly-Integrated Switched-Capacitor Power Converters, and Implementation At 48 V-12 V, 23 W/cm$^{3}$ and 93.5% Peak Efficiency

In this work a design methodology and key considerations for high-voltage and highly-integrated switched-capacitor power converters is presented. The design methodology describes the power losses in high-voltage applications, where switching losses and gate-driver losses start becoming dominant compared to fully integrated, low voltage and low power applications. The design methodology is applicable for any highly-integrated switched-capacitor topology. To verify the design methodology a 48 V-12 V ladder switched-capacitor power converter in a 180 nm SOI BCD process, with external capacitors is implemented. The floating gate-drivers and a clock controller responsible for the power switch control are also presented. The peak efficiency of the proposed power converter is measured to be 93.5 %, and 24.5 W maximum output power, resulting in a power density of 23 W/cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{3}$</tex-math></inline-formula> .

A Fully Integrated Switched Capacitor Power Converter With Minimum Driving Loss Point Tracking Technique

A fully integrated switched capacitor power converter (SCPC) with minimum driving loss point tracking (MDLPT) technique is proposed in this brief. The driving voltage, switching frequency and power switch size are all taken into consideration, and are dynamically adjusted to the optimal value. As the result, the driving loss of SCPC is optimized in real time. Digital LDO is used to detect driving loss in the proposed technique, thereby avoiding complicated search algorithms or sampling circuits. The proposed SCPC is manufactured in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18\mathbf {\mathrm {\mu }}\text{m}$ </tex-math></inline-formula> CMOS process. The input voltage is 1.8V and the output voltage is 0.5V to 1.5V, the maximum load current is 15mA. Experimental results show that the efficiency of the proposed SCPC can reach 81.9%. The proposed method can reduce the driving loss by up to 27% at typical load point, resulting in a 7.8% increase in efficiency.

A switched-capacitor power converter with unequal duty cycle for ripple reduction and efficiency improvement

This work applies unequal duty cycle to switched-capacitor (SC) dc-dc converters to improve its output ripple as well as the power conversion efficiency. By adjusting the duty cycle, the capacitor charge and discharge states are reasonably balanced. Therefore, we effectively reduce the output ripple and the charge redistribution loss, improving the efficiency. A SC converter verifies this scheme with voltage conversion ratios (VCRs) of 1/4 and 1/3, in a 65 ​nm CMOS low-power process. Operating with a switching frequency of 33 ​MHz, an input voltage of 2.4 ​V, an output range of 0.5–25 ​mA, and a VCR of 1/4, the peak efficiency increases by 1.0% and the output ripple drops by 43.6%, when compared with the equal duty cycle mode. With the input voltage equal to 1.8 ​V and the VCR ​= ​1/3, the peak efficiency increases by 0.7% and the output ripple reduces by 48.0%, compared to the equal duty cycle mode.

Current‐source mode switched‐capacitor power converters with improved current gain capability

A new family of current-source (CS) mode switched-capacitor (SC) power converters has been proposed in this study, which imposes an alternative solution for power converters especially for CS systems. The conversion ratio of this type converter is analysed and verified here to have one increased degree of freedom using the switching mode and the capacitor-tapping mode, which is a good solution to deal with the limitation of duty cycle adjustment. This research improves the CS mode system that is relatively unexplored in previous works and the proposed work fills the research gap by the sides of the well-established voltage-source (VS) system. An interesting power conversion ratio formulation is obtained, which can produce the wide range of conversion ratio of VS mode switched-inductor power converters and CS mode SC power converters in buck, boost and buck-boost versions. In addition, this proposed CS mode SC power converters have high efficiency of power conversion through simulation and prototype experiments verification. These CS mode converters can flexibly supply power directly to the load powered by the CS and successfully replace the VS mode converters operated under the current environment system.

Design of Monolithic All-NMOS Three-Level Three-phase Switched-Capacitor Power Converter for Industrial Environmental Sensor Conditioning

This article presents a fully integrated, high conversion ratio, three-level switched-capacitor (SC) power converter. The converter adopts a tri-mode operation in contrast to classic dual-mode operation in conventional SC converters. The unique circuit structure and operation create an inherent third power rail, which facilitates the use of low-voltage devices at high supply voltage for fast speed and low-silicon real estate. The tri-mode operation naturally matches a three-phase interleaving scheme for improved output voltage ripple and transient response. Implemented on a 0.35-&#x03BC;m BCD process, the design prototype accomplishes a conversion ratio greater than 4:1 and a maximum power delivery of 180 mW at 6-V input and a switching frequency of 93 MHz. With the efficient use of on-chip power switches and capacitors, it achieves a maximum power density of 125 mW&#x002F;mm².

Algorithmic Voltage-Feed-In Topology for Fully Integrated Fine-Grained Rational Buck–Boost Switched-Capacitor DC–DC Converters

We propose an algorithmic voltage-feed-in (AVFI) topology capable of systematic generation of any arbitrary buck–boost rational ratio with optimal conduction loss while achieving reduced topology-level parasitic loss among the state-of-the-art works. By disengaging the existing topology-level restrictions, we develop a cell-level implementation using the extracted Dickson cell (DSC) and charge-path-folding cell (QFC) to minimize the power-stage parasitic loss, exhibiting a Dickson-like switching pattern. The proposed partitionable main cell (MC) and auxiliary cell (AC) architecture achieves fined-grained voltage conversion ratio (FVCR) reconfiguration with optimal power cell utilization and reduced control complexity. Implemented in 65-nm bulk CMOS, the fully integrated switched-capacitor power converter (SCPC) using 10 MCs and 10 ACs executes a total of 24 VCRs (11 buck and 13 boost) with wide-range efficient buck–boost operations through the proposed reference-selective bootstrapping driver (RSBD). Based on the AVFI topology, the chip prototype reaches a measured peak efficiency of 84.1% at a power density of 13.4 mW/mm2 over a wide range of input (0.22–2.4 V) and output (0.85–1.2 V).

High-Performance Switched-Capacitor Boost–Buck Integrated Power Converters

This paper presents the design of integrated boost and buck switched-capacitor power converters with high efficiency and fast start-up time. An analysis method is determined to evaluate the key performance parameters of integrated power converters, and techniques are proposed to improve the energy conversion efficiency and the dynamic response. Boost and buck structures are modeled and compared in static and transient conditions, including the losses due to parasitic elements. A switch bootstrapping technique prevents short-circuit losses, improves driving capability and start-up time, and enhances the overall efficiency. Moreover, the application of a charge-reuse technique reduces the dynamic power losses of the integrated structures. Prototypes of the integrated power converters were fabricated in a 180-nm CMOS process. Measurement results based on the proposed techniques are presented, demonstrating the improvements in steady-state and transient characteristics with a good correlation between measured and predicted results.

A 380 V High Efficiency and High Power Density Switched-Capacitor Power Converter using Wide Band Gap Semiconductors

A 380 V High Efficiency and High Power Density Switched-Capacitor Power Converter using Wide Band Gap Semiconductors

A Switched Capacitor Energy Harvester Based on a Single-Cycle Criterion for MPPT to Eliminate Storage Capacitor

A single-cycle criterion maximum power point tracking (MPPT) technique is proposed to eliminate the need for bulky on-chip capacitors in the energy harvesting system for Internet of Everything (IoE). The conventional time-domain MPPT features ultra-low power consumption; however, it also requires a nanofarad-level capacitor for fine time resolution. The proposed maximum power monitoring does not rely on the time-domain, but on logic criterion that can be simply determined by a finite-state machine where the maximum photovoltaic (PV) power occurs at minimum conversion ratio and maximum switching frequency. Single-cycle is used as the criterion to determine the magnitude of the output power. Practical concerns, such as self-startup and self-sustaining capabilities are here addressed by proper design of the reconfigurable switched capacitor power converter. A hysteretic control not only regulates the output, but also avoids the loading condition in IoE applications. This harvester simultaneously addresses the challenges including self-startup, self-sustaining capability, and regulated output without using a storage capacitor. Compared with various PV cells, the power conversion efficiency has a peak value of 72%, which remains above 60% for a wide harvesting voltage and power range. The chip area is as small as 0.552 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

The Multilevel Switched Capacitor Power Converter. Experimental Proof of Concept.

The Multilevel Switched Capacitor Power Converter. Experimental Proof of Concept.

Topology, Modeling, and Design of Switched-Capacitor-Based Cell Balancing Systems and Their Balancing Exploration

A series of switched-capacitor (SC) cell balancing circuits is proposed for rechargeable energy storage devices like battery and supercapacitor strings in this paper. Taking a basic SC-based cell balancing unit as an equivalent resistor, the behavioral models of the proposed cell balancing circuits are developed to evaluate their balancing performance. Comparing with existing SC-based cell balancing circuits, the main advantage of the proposed circuits is that their balancing speed is independent of both of the number of battery cells and initial mismatch distribution of cell voltages. In order to improve the operation performance of SC-based cell balancing circuits in the respect of minimizing the equivalent resistance, optimizing methodologies of circuit parameters are introduced by referring the concepts of slow switching limit and fast switching limit as well as inductive switching limit of SC power converters. Simulation and experimental results are provided to verify the feasibility of the proposed cell balancing circuits.

Modeling and Analysis of Series–Parallel Switched-Capacitor Voltage Equalizer for Battery/Supercapacitor Strings

A series–parallel switched-capacitor (SC) power converter is reconfigured as a new voltage equalization circuitry for series-connected batteries or supercapacitors in this paper. The model of the new voltage equalizer is derived and successfully used to analyze the equalization speed and the energy loss. It is a very useful tool to analyze and design the SC-based equalization systems to meet different balancing speed requirements. The analysis and modeling methods can be extended to other SC-based voltage-balancing systems. A prototype is built and the experimental results are provided to confirm the theoretical analysis and the modeling method.

Single‐switch single‐inductor multi‐output pulse width modulation converters based on optimised switched‐capacitor

To combine advantages of switched-mode and switched-capacitor (SC) power converters, a series of non-isolated multi-output pulse width modulation converters are developed in this study. This type of converters employs only one inductor and one active switch, which contributes to a simple structure and easy control features. An optimised SC technique is developed for peak current limitation and equivalent resistance reduction for SC units. Circuitry configuration, operation principle, equivalent model and an optimised design are presented in detail. Experimental results of a three-output (±24 V, 48 V) converter prototype verifies the feasibility of voltage regulation and power efficiency.

A Switched Capacitor Based AC/DC Resonant Converter for High Frequency AC Power Generation

A switched capacitor based AC-DC resonant power converter is proposed for high frequency power generation output conversion. This converter is suitable for small scale, high frequency wind power generation. It has a high conversion ratio to provide a step down from high voltage to low voltage for easy use. The voltage conversion ratio of conventional switched capacitor power converters is fixed to n, 1/n or −1/n (n is the switched capacitor cell). In this paper, A circuit which can provide n, 1/n and 2n/m of the voltage conversion ratio is presented (n is stepping up the switched capacitor cell, m is stepping down the switching capacitor cell). The conversion ratio can be changed greatly by using only two switches. A resonant tank is used to assist in zero current switching, and hence the current spike, which usually exists in a classical switching switched capacitor converter, can be eliminated. Both easy operation and efficiency are possible. Principles of operation, computer simulations and experimental results of the proposed circuit are presented. General analysis and design methods are given. The experimental result verifies the theoretical analysis of high frequency AC power generation.

A 100-MHz Breakdown-Resilient Power Converter With Fully Monolithic Implementation on Nanoscale CMOS Process

A monolithic switched-capacitor power converter is designed in the nanoscale CMOS technology, employing a two-stage system architecture to mitigate overvoltage breakdown risk. The efficiency impact of various parasitic components is analyzed for design optimization on both the topology level and the device level. An external capacitorless low-dropout regulator with a wide bandwidth and a high power supply rejection ratio is introduced, removing high-frequency ripples and enabling a fast load transient response. The proposed design was implemented with the 180-nm CMOS process. At a switching frequency of 100 MHz, it regulates $V_\mathrm{out} $ at 0.8 V, with a maximum power efficiency of 60%. When the load current switches between 1.5 and 15 mA, $V_\mathrm{out} $ responds within 45 ns, with a voltage droop below 45 mV.

A Dynamic Model of Switched-Capacitor Power Converters

Switched-capacitor (SC) converters are frequently used for low-power applications that require little or no output regulation. Previous work has established static SC converter models, essentially composed of an ideal transformer (with turns ratio determined by the topology) and an output resistance that varies with component choices, switching frequency, and duty ratio. In this paper, the static model is expanded to include the dynamic response to the input voltage and output current changes. The dynamic model is particularly important in systems that experience large output power transients, such as low-power systems that enter and exit sleep modes. For applications that are only concerned with input-output behavior, a reduced-order model that neglects internal dynamics is derived. The dynamic model is validated with both simulations and experimental results.

Design and Analysis of Dual-Mode Digital-Control Step-Up Switched-Capacitor Power Converter With Pulse-Skipping and Numerically Controlled Oscillator-Based Frequency Modulation

This paper presents a 3 V-to-5 V integrated dual-mode digital-control step-up switched-capacitor (SC) power converter. The feedback control circuit is equipped with a low-power analog-to-digital converter which monitors and feeds the output voltage to a digital controller. With light loading, the control loop operates in a pulse-skipping mode. With heavy loading, the control loop operates in a frequency modulation mode (FMM) based on a numerically controlled oscillator whose switching frequency varies from 31.25 kHz to 1 MHz. The design is fabricated in a 0.5- μm digital CMOS process. With multiplierless implementation, the controller requires a gate count of less than 300. The whole design occupies a total active area of 0.23 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . From silicon measurement, with a 330-nF external flying capacitor, the design delivers a regulated 5 V output with an output current up to 25 mA from a 3 V supply, delivering an output power greater than 100 mW. The load regulation is measured to be 0.14%. A remarkable efficiency of 80% or above on average under various loading conditions is achieved. Dynamic characteristic and stability analysis of the SC converter in the FMM are presented. Comparisons with existing designs demonstrate the excellence of the proposed design.

Low-Noise Switched-Capacitor Power Converter With Adaptive On-Chip Surge Suppression and Preemptive Timing Control

An integrated switched-capacitor (SC) power converter is presented in this paper, focusing on input current surge and switching noise suppression. By incorporating an adaptive on-chip surge suppression feedback loop, di/dt switching noise is significantly suppressed, and the start-up inrush current surge can also be greatly reduced. Furthermore, a preemptive timing control scheme is proposed to provide clock signals for each power switch with precisely controlled switching sequence and phase delays, contributing to further switching noise reduction. The proposed converter was fabricated with the AMIS 0.5-μm CMOS process. As the input varying from 2.7 to 4.2 V, the output voltage is regulated at 5 V, with a maximum load current of 25 mA. Compared to a conventional interleaved SC power converter, the proposed design demonstrates 74.7% and 80.9% reductions on the start-up inrush current surge and steady-state input current perturbation, respectively, and a 60.2% output switching noise reduction. The peak efficiency of 90.2% is measured at 2.7-V input and 100-mW load.

A Systematic USFG Design Approach for Integrated Reconfigurable Switched-Capacitor Power Converters

A systematic design approach using signal flow graph (SFG) is presented in this paper, tailored for integrated reconfigurable switched-capacitor (SC) power converters. To achieve an optimal power stage, an unified signal flow graph (USFG) model is developed. System transfer function and I/O impedance can be evaluated based on it. To verify the design approach, the paper demonstrates a step-up/down reconfigurable SC power converter with five optional gain ratios. A dual-loop control scheme is employed to reconfigure the converter according to the instantaneous line/load conditions. A low-power, digital controller is designed in the subthreshold region for the feedback control loop. The converter was fabricated with a 130-nm CMOS process. Experimental results show that its output can be continuously regulated from 0.4 to 2.2 V, while allowing the input voltage to randomly vary between 0.9 and 1.5 V. The line regulation is maintained below 1.4%, with a lowest value of 0.07%. The maximum efficiency of 90.22% is measured at 0.55-V output voltage and 20-mW load.