Switched-capacitor Power Amplifier Research Articles

A Class-G Voltage-Mode Doherty Power Amplifier

This paper presents the combination of two back-off efficiency enhancement techniques, the voltage-mode Doherty and the class-G switched-capacitor power amplifier (PA), to achieve efficiency peaking at both 6 and 12 dB back off without introducing the mode-switching glitches present in previous architectures. The proposed technique enables transmission of high peak-to-average-power ratio (PAPR) signals with high efficiency while maintaining excellent linearity. The PA is fabricated in 45-nm CMOS SOI with integrated balun for power combining and matching. At 3.5 GHz a saturated output power of 25.3 dBm is measured with 30.4%/25.3%/17.4% power added efficiency (PAE) at 0/6/12 dB back off. With memoryless, non-adaptive linearization, the PA achieves 19.2% PAE with −35.8 dB error vector magnitude (EVM) while transmitting a 40 MHz 256-QAM 10.1 dB PAPR 802.11ac modulation. Significant efficiency improvement compared to class-B and EVM better than −34 dB is maintained over more than 1 GHz bandwidth.

A Multiphase Switched Capacitor Power Amplifier

This paper presents an all-digital multiphase switched capacitor power amplifier (MP-SCPA) implemented in a 130-nm CMOS. Quadrature architectures suffer reduced output power and efficiency owing to the combination of out-of-phase signals. The MP architecture reduces the phase difference between the basis vectors that are combined, and hence the output power and efficiency are greatly improved. Sixteen clocks with identical adjacent phase separations are produced by a phase generator with each phase’s relative amplitude weighted on the top plate of a capacitor array and combined on a common bottom plate, resulting in linear amplification. The MP-SCPA delivers a peak output power $P_{\mathrm{ out}}$ of 26 dBm with a peak system efficiency (SE) of 24.9%. When amplifying a long-term evolution signal at 1.85 GHz, the average $P_{\mathrm{ out}}$ and the SE are 20.9 dBm and 15.2%, respectively, with an Adjacent Channel Leakage Ratio (ACLR) < −30 dBc and error vector magnitude of 3.5% rms using a 2-D digital predistortion.

Analysis and design of power and efficiency in third-order matching networks for switched-capacitor power-amplifiers

This paper presents the design of a matching network (MN) for switched-capacitor PAs (SCPA) optimized for efficiency against required load output power. The presented third-order MN exploits the intrinsic output capacitance of the SCPA, reducing the number of passive components required by the MN. As an example, a MN for a 1.1 V switched capacitor power amplifier has been designed with a bluetooth application in mind. The example MN has been implemented in a 28 nm CMOS RF metal stack and provides 16.7 dBm output power with IL = 1.1 dB at 2.4 GHz in an area of 300 × 300 μm2 when resonated by an SCPA capacitance of 2.3 pF. Further structures have then been implemented and characterized, covering a broader set of applications.

A Quadrature Switched Capacitor Power Amplifier

This paper presents an all-digital class-G quadrature switched-capacitor power amplifier (Q-SCPA) implemented in 65 nm CMOS. It combines in-phase ( I ) and quadrature ( Q ) signals on a shared capacitor array. The I / Q signals are digitally weighted and combined in the charge domain. Quadrature summation results in a 3 dB signal loss; Hence the Q-SCPA utilizes a class-G dual-supply architecture to improve efficiency at backoff. Unlike polar/EER counterparts, the Q-SCPA requires no wideband phase modulator or delay matching circuitry. The Q-SCPA delivers a peak output power of 20.5 dBm with a peak PAE of 20%. It is measured with a 10 MHz, 64 QAM LTE signal, and achieves an ACLR of $ , with an ${\bf EVM} 4%-rms.

Clover shape layout technique in switched capacitor power amplifier for improving drain efficiency

Clover shape layout technique in switched capacitor power amplifier for improving drain efficiency

A Class-G Switched-Capacitor RF Power Amplifier

A switched-capacitor power amplifier (SCPA) that realizes an envelope elimination and restoration/polar class-G topology is introduced. A novel voltage-tolerant switch enables the use of two power supply voltages which increases efficiency and output power simultaneously. Envelope digital-to-analog conversion in the polar transmitter is achieved using an SC RF DAC that exhibits high efficiency at typical output power backoff levels. In addition, high linearity is achieved and no digital predistortion is required. Implemented in 65 nm CMOS, the measured peak output power and power-added efficiency (PAE) are 24.3 dBm and 43.5%, respectively, whereas when amplifying 802.11g 64-QAM OFDM signals, the average output power and PAE are 16.8 dBm and 33%, respectively. The measured EVM is 2.9%.

Digital power amplifier: A new way to exploit the switched-capacitor circuit

A digital power amplifier (DPA) that uses switched-capacitor circuits in 90 nm CMOS to efficiently amplify signals with large peak-toaverage power ratios is described in this article. In traditional DPAs, a digital code word representing a desired output envelope voltage is used to control a combination of wide-dynamic range current sources. In contrast, the switched-capacitor power amplifier (SCPA) provides a linear output characteristic by using the digital code word to selectively switch or not switch a bank of integrated capacitors at the RF carrier frequency. Therefore, the SCPA combines the functionalities of an envelope DAC and a power amplifier, and achieves excellent efficiency and output power levels. The SCPA benefits from CMOS transistor scaling, which makes RF SOC integration realizable.

&lt;/title&gt; &lt;/titles&gt; &lt;publication_date&gt; &lt;month&gt;12&lt;/month&gt; &lt;year&gt;2011&lt;/year&gt; &lt;/publication_date&gt; &lt;pages&gt; &lt;first_page&gt;3174&lt;/first_page&gt; &lt;last_page&gt;3174&lt;/last_page&gt; &lt;/pages&gt; &lt;publisher_item&gt; &lt;item_number item_number_type='arNumber'&gt;6084865&lt;/item_number&gt; &lt;/publisher_item&gt; &lt;doi_data&gt; &lt;doi&gt;10.1109/JSSC.2011.2176997&lt;/doi&gt; &lt;resource&gt;http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6084865&lt;/resource&gt; &lt;/doi_data&gt; &lt;/journal_article&gt; &lt;journal_article&gt; &lt;titles&gt; &lt;title&gt;&lt;![CDATA[A Switched-Capacitor RF Power Amplifier

A fully integrated switched-capacitor power amplifier (SCPA) utilizes switched-capacitor techniques in an EER/Polar architecture. It operates on the envelope of a nonconstant envelope modulated signal as an RF-DAC in order to amplify the signal efficiently. The measured maximum output power and PAE are 25.2 dBm and 45%, respectively. When amplifying an 802.11g 64-QAM orthogonal frequency-division multiplexing (OFDM) signal, the measured error vector magnitude is 2.6% and the average output power and power-added efficiencies are 17.7 dBm and 27%, respectively.