Switched-Capacitor Multilevel Research Articles

Single Source Switched Capacitor Multilevel inverter with Voltage Boosting Capability and Low Switch Count

Single Source Switched Capacitor Multilevel inverter with Voltage Boosting Capability and Low Switch Count

A Voltage-Boosting Seven-Level Switched Capacitor Multilevel Inverter With Reduced Device Count

A Voltage-Boosting Seven-Level Switched Capacitor Multilevel Inverter With Reduced Device Count

Design of Switched Capacitor Multilevel Inverter with Selective Harmonic Elimination

In this paper, Selective Harmonic Elimination (SHE) technique is applied to control multilevel inverters that can be used to eliminate the low order dominant harmonics. This is considered a low frequency technique, in which the switching angles are predetermined based on solving a system of transcendental equations. Newton Raphson is one among the heuristic techniques utilised for selective harmonic elimination. The proposed SHE strategy is simulated along with Sinusoidal Pulse Width Modulation (SPWM) technique and the harmonic distortions are measured and compared for both techniques in MATLAB/Simulink software.

Design and Flight Qualification of a Flying Capacitor Multilevel Converter for Electric Aircraft Applications

Multilevel switched-capacitor converters, such as the flying capacitor multilevel (FCML) converter, offer high energy density and efficiency, over a wide voltage range, making them suitable for applications in electrified aircraft. However, concerns of reliability due to the increased number of active and passive components have limited the use of high-level count converters in aircraft applications. This work addresses the challenges of designing a high-level count converter with the goal of extremely high efficiency and power density, with maintained reliability and flight readiness. We present detailed component selection and design techniques to achieve this goal, along with a high-performance 28.2 kW/kg, 99.52% efficient high-voltage dc-dc step-up power converter for experimental validation. Finally, we demonstrate successful completion of critical flight qualification testing of the hardware prototype, including thermal, shock and vibration.

Modelling of Symmetric Switched Capacitor Multilevel Inverter for High Power Appliances

Modelling of Symmetric Switched Capacitor Multilevel Inverter for High Power Appliances

Development and Control of a Switched Capacitor Multilevel Inverter

This article offers a novel boost inverter construction with a Nine-level quadruple voltage boosting waveform. The primary drawback of conventional MLI is the need for a high voltage DC-DC converter to increase the voltage when using renewable energy sources. Consequently, the developed method, complete with a quadruple voltage boost ability, can alleviate that shortcoming by automatically increased the incoming voltage. A single DC source, two switching capacitors, and eleven switches are all that are used in the newly presented architecture. The voltage of the capacitor automatically balances. The switched capacitor MLI is distinguished by the fewer parts that are required and the substitution of a capacitor for a DC source. The switching capacitor has to be charged and discharged properly in order to produce the nine-level output voltage waveform. The SPSC unit makes these levels attainable. To achieve voltage boosting, switched capacitors are coupled in parallel and series in the conduction channel. The quality of this proposed topology has been analyzed through different parameters based on the components count, THD, and cost; the resulting efficiency reaches 97.85%. The switching order of the proposed method has been controlled by the Nearest Level Modulation Method (NLC). MATLAB and PLECS software were used to evaluate the constructed Nine-level converter.

An I-Network Switched Capacitor Multilevel Inverter (INSC-MLI) Topology with Reduced Switch Count and its SV-PWM based control algorithm

An I-Network Switched Capacitor Multilevel Inverter (INSC-MLI) Topology with Reduced Switch Count and its SV-PWM based control algorithm

Multilevel Switched-Capacitor AC–DC Step-Down Rectifier for Wireless Charging With Reduced Conduction Loss and Harmonic Content

In this article, a wireless charging architecture employing a multilevel switched-capacitor (MSC) ac–dc rectifier is investigated. The proposed MSC rectifier features a multilevel design that is scalable to accommodate different power ratings and load ranges. The topology showcases advantages for wireless power transfer (WPT) systems in terms of compactness, efficiency, impedance tunability, and harmonic attenuation. The single-stage active topology is capable of varying its low-distortion staircase input voltage to tune the WPT system for high system-wide efficiency. A seven-level, 20-W prototype is used to verify the WPT loading and loss analysis. The prototype operates at 150 kHz with up to 3:1 step-down conversion ratio to an output voltage of 5.0 V. The experimental peak dc-to-dc efficiency is 93.8% and the rectifier peak efficiency is 98.3%. The rectifier demonstrates low waveform distortion and high efficiency across many WPT loading conditions, solidifying its place as a strong candidate for wireless power applications.

Self-Balanced Twenty Five Level Switched Capacitor Multilevel Inverter With Reduced Switch Count and Voltage Boosting Capability

Multilevel inverters (MLI) are gaining wider popularity owing to their increasing power handling capability and improving power quality output. With an inclining trend towards renewable energy utilization, they find a vital application in wind and solar power generation systems. This article proposes a new multilevel dc–ac inverter. The proposed MLI produces a twenty five level output and offers an inherent capacitor self-balancing capability. The inherent self-balancing eliminates the requirement of auxiliary sensor circuit or capacitors voltage balancing algorithms. Dual asymmetric voltage sources and switched capacitors along with their proper charging/discharging pattern are utilized for the generation of output levels. A voltage gain of 2 and a total standing voltage (TSV) of 10 is achieved though the proposed inverter. In order to realize the merit of the proposed MLI over recently developed topologies, a comparative analysis in terms of system components such as numbers of power electronic switches, gate driver circuits, diodes, and capacitors as well as system parameters such as voltage gain, TSV and power loss is presented. The proposed MLI is developed in the laboratory and is controlled through the digital signal processor TMS320F28379D using nearest level control technique. The experimental results are acquired for different loads and under varying modulation index to validate the feasibility of the proposed inverter.

A Symbiotic Organism Search-Based Selective Harmonic Elimination in a Switched Capacitor Multilevel Inverter

Multilevel inverters are increasingly being employed for industrial applications, such as speed control of motors and grid integration of distributed generation systems. The focus is on developing topologies that utilize fewer lower-rating switches and power sources while working efficiently and reliably. This work pertains to developing a three-phase multilevel inverter that employs switching capacitors and a single DC power supply that produces a nine-stage, three-phase voltage output. A recently proposed powerful meta-heuristic technique called symbiotic organism search (SOS) has been applied to identify the optimum switching angles for Selective Harmonic Elimination (SHE) from the output voltage waveform. A thorough converter analysis has also been done in the MATLAB/SIMULINK environment and is validated with the real-time hardware-in-the-loop (HIL) experiment results.

A new generalized cross-connected switched capacitor multilevel inverter topology with high output voltage gain for single phase solar PV unit

Switched capacitor multilevel inverters are gaining much attention these days due to their merits like voltage boosting and voltage balancing characteristics. A Cross Connected Switched Capacitor Multilevel Inverter (C2SC-MLI) topology is proposed in this work. It can synthesize thirteen levels in the terminal voltage waveform and with a voltage boost ratio of 1:3. The topology is extendable by adding additional “n” modules in series. The number of levels (NLevel) and the voltage gain can be increased up to 4i+9 and 1:(i+2) respectively by connecting ‘i’ such ‘n’ modules. The topology also has inherent voltage balancing ability. To prove the advantage of proposed topology it is compared with recent switched capacitor multilevel inverter topologies and conventional multilevel inverter topologies in terms of number of power electronic components required, cost and voltage gain. The performance of proposed topology is validated using simulation in MATLAB and with an experimental prototype rated 0.1 kW fed by a solar PV emulator under steady state and dynamic loading conditions.

A 7-Level Switched Capacitor Multilevel Inverter With Reduced Switches and Voltage Stresses

This brief presents a novel switched-capacitor multilevel inverter (SCMLI). The inverter can produce a 7-level output voltage utilizing a dc source, nine switches, two series-connected diodes, and three capacitors. The capacitors are charged from the supply voltage directly by turning on appropriate switching states. The proposed structure realizes all the output voltage levels without an H-bridge circuit at the load-end. A detailed comparison study with other similar inverters has been presented. It shows that the proposed SCMLI requires a lower number of components and is more cost-effective as compared to other inverters. The circuit build-up, capacitor charging process, operating principle, voltage stress analysis, and capacitor selection procedure of the proposed inverter is presented in detail. Finally, an extensive experimental study validates the performance and effectiveness of the proposed inverter.

Generalized Structures for Switched-Capacitor Multilevel Inverter Topology for Energy Storage System Application

The apparent advantages of Multilevel Inverter (MLI) topologies in handling medium and high power with less loss in switching and lower harmonic distortion in an output voltage waveform makes it better than the conventional inverter. However, the MLI topologies utilize a large number of DC power supplies and power semiconductor devices. They also have a higher value of total standing voltage (TSV). Moreover, capacitor voltage balancing problems, self-voltage boosting inability, and complex control techniques require a relook and improvement in their structure. More recently, Switched-Capacitor Multilevel Inverter (SCMLI) topologies have been proposed to overcome the shortcomings of MLIs. In this paper, a generalized structure for a single-phase switched capacitor multilevel inverter (SCMLI) with self-voltage boosting and self-voltage balancing capability is proposed. A detailed analysis of a general structure of SCMLI is presented. The comparative analysis of the structures is carried out with recently reported topologies to demonstrate superiority. An optimized low-frequency modulation controls the output voltage waveform. The simulation and experimental results are included in the paper for single-unit symmetric (9-level voltage) and asymmetric (17-level voltage) configurations.

An Efficient Asymmetric Direct Current (DC) Source Configured Switched Capacitor Multi-level Inverter

This paper is dealing about Switched Capacitor Multi-Level Inverter (SCMLI) circuit which is controlled by triangular multicarrier Sinewave Pulse Width Modulation (SPWM) technique. The proposed SCMLI is powered from asymmetric DC source configuration to obtain multi-level output voltage by applying switching pulse to the main circuit from control circuit for switching operation. Fourteen switches and four capacitors are employing to do the proposed inversion operation in an effective way. Switching capacitors can perform boost operation to enhance voltage from the source level to the required level. Input DC from the asymmetric sources is converted to AC voltage for the application of consumers. This proposed conversion system is applicable for mainly in industrial and renewable energy-based energy conversion system because it can carry high output voltages. This proposed method gives about more efficiency. Also reduces switching losses in lower value, low conduction losses and capacitor ripple losses. The simulation model is analyzed in MATLAB/SIMULINK platform and the same validated in hardware results. The developed SCMLI structure is witness over other topologies for the power inversion process in the multi-level.

Investigation on Fault Tolerant Capability of a Single Source Switched Capacitor Multilevel Inverter

Maintaining the proper performance of inverters in various applications is crucial for preventing the detrimental consequences of systems' failure. This article investigates the fault tolerance of a switched capacitor multilevel inverter, which has redundant switching states for each output voltage level, in both open-circuit and short circuit faults. In each case, given the type of fault and associated switch, new switching algorithms are proposed to maintain the output voltage levels. Also, the appropriate performance of the converter in postfault conditions is considered. Finally, to ensure the accuracy of the converter performance and switching algorithms in normal and postfault performance states, the structure is implemented and experimental results are presented.

A Highly Linear Multi-Level SC DAC in a Power-Efficient Gm-C Continuous-Time Delta-Sigma Modulator

A highly linear multi-level switched-capacitor (SC) digital-to-analog converter (DAC) is proposed for continuous-time delta-sigma modulators (CTDSMs). A Gm-C CTDSM with a passive frontend low-pass filter (LPF) is further proposed to mitigate the problems of increased settling requirements and worsened anti-aliasing capability (consequences of an SC DAC) so as to realize an extremely power-efficient CTDSM. A 100-kHz bandwidth $40\times $ oversampling 3rd-order CTDSM prototype employing the proposed DAC and modulator topology is fabricated in a low-leakage 65-nm CMOS technology. Experimental results show that the modulator achieves a spurious-free dynamic range (SFDR), dynamic range (DR) and signal-to-noise and distortion ratio (SNDR) of 86.6 dB, 85.1 dB and 78.8 dB, respectively. To the best of our knowledge, this is the first silicon-proven CTDSM with a more-than-3-level DAC that leads to an excellent SFDR while not requiring dynamic element matching, component calibration, precise reference voltages, or an operating frequency higher than the modulator’s sampling frequency ${{f}}_{{{s}}}$ . The prototype consumes 22.8 $\mu \text{W}$ from a 1.2-V supply, amounting to a Walden’s and Schreier’s figure of merit (FoM) of 16 fJ/conv.-step and 181.5 dB, respectively, which is the best among state-of-the-art CTDSMs. It further achieves high alias rejections of 52 dB and 58 dB at ${{f}}_{{{s}}}$ and $2{{f}}_{{{s}}}$ , respectively, and can tolerate a clock period jitter of 3 ns.

Compact Switched Capacitor Multilevel Inverter (CSCMLI) With Self-Voltage Balancing and Boosting Ability

This letter presents a compact switched capacitor multilevel inverter (CSCMLI) topology with reduced switch count and with self-voltage balancing and boosting ability. The operational mode of the proposed CSCMLI is discussed. A comparative analysis in terms of number of switches and blocking voltages is presented against recent switched capacitor multilevel inverter topologies. Further to enhance the quality of the output voltage, a new level shifted multicarrier pulsewidth modulation (PWM) technique is recommended. This modulation technique produces low THD and high rms voltage. The proposed modulation technique is implemented in the nine-level CSCMLI with single dc source and two capacitors. The simulated and experimental results are verified for a switching frequency of 50 Hz and 2.5 kHz using the proposed PWM control.

An Asymmetric Switched Capacitor Multilevel Inverter With Component Reduction

This paper proposes a new switched capacitor (SC-Type) inverter for asymmetrical multilevel inverters (MLIs) with fewer components. In order to balance the voltages of the capacitors, the proposed topology uses a special method to charge/discharge the capacitors. In the proposed inverter, the number of switches, the number of dc voltage sources, the amount of blocked voltage in the switches, and the power losses are reduced. Fewer components result in lower size, complexity, and cost of MLI. Cascade connection of the proposed topology is used to achieve a higher number of output voltage levels. The MATLAB simulations and experimental results of a 25-level MLI verify the good performance of the proposed inverter.

Step-up Switched Capacitor Multilevel Inverter with a Cascaded Structure in Asymmetric DC Source Configuration

Step-up Switched Capacitor Multilevel Inverter with a Cascaded Structure in Asymmetric DC Source Configuration

Evaluation of Impedance network Based 7-Level Switched Capacitor Multi Level Inverter for Single Phase Grid Integrated System

In this paper, a single phase impedance network based symmetrical Multi Level Inverter (MLI) integrated to grid is presented. The proposed topology requires a reduced number of controlled switches as compared to voltage source and impedance source MLI’s. The complexity, switching losses and size decreases due to reduced number of switch count. A simple Self-Voltage Balancing Circuit technique is used for maintaining equal voltage across all DC-link capacitors. Impedance network is used for boosting the voltage so as to meet the load/grid voltage. In order to synchronize the proposed inverter with grid two control loops are used. The first loop is voltage controller, which controls the output voltage of impedance network and the second loop is a current control loop, it injects the desired current into the grid. Proposed Impedance network based Switched Capacitor MLI (ISCMLI) performance in stand-alone and with grid integration is analyzed with MATLAB/SIMULINK and to validate the performance of proposed ISCMLI a proto model is developed.