Switched-capacitor Integrator Research Articles

A Speed-Enhancement Technique Based on Single-Node-Detection and Bulk-Driven for Inverter-Based Amplifier in Switched-Capacitor Integrator

A Speed-Enhancement Technique Based on Single-Node-Detection and Bulk-Driven for Inverter-Based Amplifier in Switched-Capacitor Integrator

A 10-kHz BW 104.3-dB DR discrete-time delta-sigma modulator with ring-amplifier-based integrator

This paper presents a 3rd-order discrete-time delta-sigma modulator (DT DSM) with ring-amplifier-based integrators. To fulfill the performance requirement of the switched-capacitor (SC) integrator for the DSM with low power consumption, a dynamic ring amplifier is employed to replace the conventional continuous-time operation transconductance amplifier (OTA) in the integrator. The offset and 1/f noise of the 1st-stage integrator are further suppressed with an auto-zero structure. The quantizer is realized by a 3-bit flash analog-to-digital converter (ADC) to reduce the quantization noise power, while the mismatch in the feedback digital-to-analog converter (DAC) is suppressed by a dynamic weighting averaging (DWA) circuit. The DT DSM prototype is fabricated with a 0.18-μm CMOS process with an active area of 1.39 mm2, achieving 99.3 dB SNDR and 104.3 dB DR with a signal bandwidth of 10 kHz and an oversampling ratio of 128. The power consumption is 963.9 μW under a 3.3V power supply, corresponding to a Schreier figure-of-merit(FoMs) value of 174.5 dB.

A 600-MS/s, 65-dB SNDR, 75-MHz BW Time-Interleaved Noise-Shaping SAR ADC

A time-interleaved noise-shaping (TINS) successive approximation register (SAR) analog-to-digital converter (ADC) for wide bandwidth, high resolution, and low power consumption is proposed. A fully passive switched-capacitor integrator based on a single capacitor and a single-input comparator is adopted in the proposed three-channel structure for 1st-order noise shaping with low power consumption. The SAR conversion is split into coarse and fine conversions to allow noise shaping in the time-interleaved structure to maximize the bandwidth. In addition, a dynamic weight averaging method for three channels is introduced to suppress the effect of capacitor mismatch. The prototype ADC is implemented in a 28-nm CMOS process and achieves a signal-tonoise and distortion ratio of 65.37 dB, a bandwidth of 75 MHz at a sampling rate of 600 MHz, and a power consumption of 4.015 mW with a 1.1 V supply. A Walden figure-of-merit (FoM) of 17.65 fJ/conv.-step and a Schreier FoM of 168.1 dB show that the proposed TINS SAR ADC improves speed and accuracy with good power efficiency.

Optimization of Slew Mitigation Capacitor in Passive Charge Compensation-Based Delta–Sigma Modulator

In this paper we propose a scheme of optimizing the size of charge compensation (CC) capacitor in a delta-sigma modulator (DSM) using a passive charge compensation (PCC) based switched capacitor integrator (SCI). The slewing behavior of a PCC based SCI is analyzed in both integration phase (IP) and sampling phase (SP) to optimize the size of CC capacitor. The effectiveness of the proposed scheme is demonstrated by implementing a 2-1 cascaded DSM using PCC based SCI with optimized value of CC capacitor in 0.18-μm CMOS technology. The DSM operates at a frequency of 5-MHz and achieves a peak SNDR of 103.1-dB in the audio bandwidth of 20-kHz. The power consumption of DSM is 220-μW at a supply voltage of 0.85-V and it consumes 1.3 mm of area. Post-layout simulations show an improvement of 10.8-dB in the SNDR of DSM by using the optimized value of CC capacitor in PCC based SCI.

A chopper amplifier with a low duty‐cycle sub‐sampling in the switched‐capacitor integrator for noise reduction

AbstractThis letter presents a low‐noise implementation of the switched‐capacitor (SC) DC servo loop (DSL) in the capacitively coupled chopper instrumentation amplifier (CCIA). The noise of the SC integrator in SC DSL is first analyzed, then a low duty‐cycle subsampling and unbalanced capacitor ratio are proposed to reduce the noise. Fabricated in a 65‐nm complementary metal‐oxide semiconductor (CMOS) process, the CCIA achieves 2.5 μVrms input‐referred noise, integrated from 0.5 to 250 Hz, and 110‐mV electrode‐DC offset (EDO) cancellation range. Besides, the calculated noise of the SC integrator well matches the measured, which proves the noise analysis. Compared with prior designs adopting similar SC integrators, this work reduces the noise level by 2× and increases the cancellation range by 2×.

A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC

This brief presents a single-loop third-order discrete-time delta-sigma ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {\Delta } {\Sigma }$ </tex-math></inline-formula> ) analog-to-digital converter (ADC). The proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {\Delta } {\Sigma }$ </tex-math></inline-formula> ADC employs source-follower (SF)-based open-loop switched-capacitor (SC) integrators to achieve high-speed operation with efficient power consumption. A modified feed-forward topology is proposed to improve the linearity of the modulator using the SF-based integrators. An interpolating 4-bit flash quantizer with an embedded data weighted averaging (DWA) function is employed to address the nonlinearity of the feedback digital-to-analog converter (DAC) for high speed operation. The prototype ADC implemented in a 65nm CMOS technology achieves 75.4-dB dynamic range (DR) and 73.3-dB peak signal-to-noise-and-distortion ratio (SNDR) over 10-MHz bandwidth with an oversampling ratio (OSR) of 16. The power consumption of the modulator is 13.3-mW from a 1.1-V supply, resulting in the Walden and Schreier figure-of-merits (FoMW and FoMS) of 174-fJ/conversion-step and 164-dB, respectively.

A Single-Bit Incremental Second-Order Delta-Sigma Modulator with Coarse-Fine Input Buffer

This paper presents an incremental second-order delta-sigma modulator with a coarse-fine input buffer in 180-nm CMOS. The modulator’s architecture was implemented as a second-order cascade of integrators with a feedback structure. The switched-capacitor integrator was operated in discrete time, with high-gain amplifiers required to achieve improved performance during the integration phase. The amplifier comprised rail-to-rail input and gain-boosted cascode intermediate stages, thus achieving a high gain and wide input voltage range. The circuit adopts a coarse-fine buffer for higher performance. The coarse buffer is operated first to enable fast settling through a high slew rate, followed by the fine buffer to satisfy the low-noise and high-accuracy characteristics. The fine buffer has a smaller current consumption with higher power efficiency. The experiment results show that the proposed input buffer achieved a 13.14 effective number of bits and an 80.87 dB signal-to-noise and distortion ratio. The modulator operates a single bit and sampling clock at 125 kHz. The proposed delta-sigma modulator was operated at 1.8 V. The proposed circuit was designed using a standard 0.18-μm CMOS process with an active area of 1.06 mm2. The total current consumption with the coarse-fine buffer was 1.374 mA.

Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

A circuit-level inverter-based switched capacitor integrator model justified by post-layout simulations of an incremental sigma-delta converter

This paper proposes a circuit-level model of an inverter-based switched-capacitor (SC) integrator involved in a previously published incremental sigma-delta analog-to-digital converter (I $$\Sigma {\Delta }$$ ADC) to explain the ADC resolution degradation observed in the post-layout simulation. A fine analysis of post-layout signals led to a new model of the integrator with parasitic capacitors. Then the model has been included in the I $$\Sigma {\Delta }$$ ADC model, which has been simulated with Matlab. To get detailed results and be able to handle comparisons, various calibration techniques have been applied to the I $$\Sigma {\Delta }$$ ADC outputs coming from post-layout simulation and from the new model so that a better resolution is achieved. The results show a good likeness of the error shapes and magnitudes for the new model compared to post-layout simulations. We deduce that the proposed model is a good representation of the degradation phenomena, this with a high level of confidence.

Performance Enhancement of Capacitive-Type Torque Sensor by Using Resonant Circuit

This article proposes a method for improving the resolution of a capacitive-type (C-type) torque sensor. This method amplifies the output signal variation of a capacitance-to-digital (CDC) chip by designing a series-resonant circuit. This study considers the data sampling method of the CDC chip and the effects of the resonant circuit on the output signal. The CDC chip employs a switched-capacitor (SC) integrator for data sampling. The SC integrator was simulated to estimate the amplification of the output signal by the resonant circuit. The inductance and resistance of the resonant circuit are designed to optimize the sensor performance. As the SC integrator is commonly used in CDC chips, the proposed method is adaptable to a majority of existing C-type sensors. When fabricating the sensor, it is important to obtain the designed capacitance for implementing the resonant circuit. We design printed circuit board structures that can accurately obtain the designed gap between sensor electrodes and the ground. Artificial neural network is used for sensor calibration process. To prove the effectiveness of these methods, the performance of a sensor equipped with the resonant circuit was compared to that of a previously developed sensor.

A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications

A novel switched-capacitor integrator based programmable resolution analog to digital converter (ADC) architecture is proposed. The proposed hybrid ADC architecture can be switched between successive approximation register (SAR) and delta-sigma modulator (DSM) mode in 8-bit to 15-bit resolution. A mathematical relationship showing the effect of mismatch of capacitors on ADC linearity is derived. A fully differential folded cascode operational transconductance amplifier (OTA) operating in a weak inversion region is designed using gm/ID technique with programmable unity gain bandwidth and slew rate. The designed OTA offers 83 dB DC gain. The proposed ADC, designed and laid out in UMC 180 nm standard CMOS technology, occupies an area of 0.228 mm2. The ADC resolution is programmable from 8-bit to 15-bit using a 3-bit control bus (res[2 : 0]). The hybrid ADC operates in SAR mode from 8-bit to 11-bit resolutions and as the first-order DSM with a multi-bit quantizer in 12-bit to 15-bit resolutions. The dynamic performance of the proposed ADC is verified through post-layout simulations with a supply voltage of 1.8 V. It exhibits a signal-to-noise and distortion ratio of 45–86 dB and consumes a power of 0.86–98 μW across target resolutions (8–15 bits).

100.5 dB SNDR Analog Front-End With a Resistor-Based Discrete-Time Delta-Sigma Modulator for Eliminating Switching Noise and Harmonics

This paper presents a high-resolution analog front-end (AFE) circuit operating in the 25 kHz signal bandwidth. The AFE consists of a capacitively-coupled chopper instrumentation amplifier (CCIA) and a third-order delta-sigma modulator (DSM). Signal distortion often occurs at the junction of CCIA and DSM, so the resistor-based discrete-time DSM (RB DT–DSM) is proposed to solve this problem. Both conventional DT–DSM and the proposed RB DT–DSM are designed and compared through simulations and chip measurements. When a conventional DT–DSM is used, a switched-capacitor integrator with a large capacitor and switch are connected to the CCIA output node, so large switching noise, significant charge injection, and a long settling time occur at the CCIA output, resulting in harmonic distortions. Therefore, CCIA requires more power consumption to reduce the settling time for conventional DT–DSM architectures. On the other hand, when the proposed RB DT–DSM is used, only a resistor and a small switch are connected to the CCIA output. Due to this novel interface technique, the switching noise is very small at the CCIA output, and the settling of the CCIA becomes fast. As a result, it is possible to effectively eliminate harmonic distortions while reducing the power requirement of the CCIA. Both the conventional and proposed AFE circuits were manufactured by a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> complementary metal-oxide-semiconductor (CMOS) process. The conventional AFE shows a peak SNR of 101.1 dB and a peak SNDR of 91.2 dB. The proposed AFE with RB DT–DSM shows a peak SNR of 101.3 dB and a peak SNDR of 100.5 dB, which verifies the significant reduction in harmonic distortions.

Low-Power Small-Area Inverter-Based DSM for MEMS Microphone

A delta-sigma modulator (DSM) is proposed for the direct connection to micro-electro-mechanical systems (MEMS) microphone. To reduce power, both the DAC reference voltage (VREF) and the DSM supply voltage (VDD) are reduced to 700 mV by limiting the maximum linear acoustic input range to 110 dB SPL (sound pressure level). For the low VDD operation, the switched capacitor (SC) integrators of DSM employ CMOS inverters as amplifiers. A unity-gain buffer compensates the pole error of the SC integrator; it reduces chip area by replacing the auto-zero capacitor of conventional inverter-based SC integrator. Compared to the conventional integrator, the integrator of this brief reduces the pole error from 0.3% to 0.06%, reduces the chip area and the power by 32.4% and 24.8%, respectively. The 3rd order DSM in a 65 nm CMOS process was measured to have Walden-figure of merit (FoMw) 89.3fJ/step, dynamic range (DR) 90.1 dB, signal-to-noise ratio (SNR) 87.2 dB, signal-to-noise and distortion ratio (SNDR) 86.4 dB, and power 122 uW at 10 MHz clock frequency (Fs).

A Low-Noise Chopper Amplifier with Offset and Low-Frequency Noise Compensation DC Servo Loop

The low-frequency and low-amplitude characteristics of neural signals poses challenges to neural signals recording. A low noise amplifier (LNA) plays an important role in the recording front-end. A chopper-stabilized analog front-end amplifier (FEA) for neural signal acquisition is presented in this paper. It solves the noise and offset interference caused by the servo loop in the chopper amplifier structure. The proposed FEA employs a switched-capacitor (SC) integrator with offset and low-frequency noise compensation. Moreover, a dc-blocking impedance is placed for ripple-rejection (RR), and a positive feedback loop is employed to increase input impedance. The proposed circuit is design in a 0.18-µm 1.8-V CMOS process. It achieves a bandwidth of up to 9 kHz for local field potential and action potential signals acquisition. The referred-to-input (RTI) noise is 0.72 µVrms in the 1 Hz~200 Hz frequency band and 3.46 µVrms in the 200 Hz~5 kHz frequency band. The noise effect factor is 0.43 (1 Hz~200 Hz) and 2.08 (200 Hz~5 kHz). CMRR higher than 87 dB and PSRR higher than 85 dB are achieved in the entire pass-band. It consumes a power of 3.96 µW/channel and occupies an area of 0.244 mm2/channel.

A 2 nW 0.25 V 140 dB-FOM Inverter-Based First Order ΔΣ Modulator

In this brief, we introduce an ultra-low voltage, ultra-low power, inverter-based, discrete-time, 1st order ${\Delta } {\Sigma }$ modulator. It exploits an original switched-capacitor integrator to achieve interesting performances with supply voltages as low as 0.25 V. It also employs a clock-boosting technique to improve pass-gate operation. A prototype has been designed and produced using a 0.18 $\mu \text{m}$ CMOS process by UMC. The modulator reaches an SNDR of 37.2 dB at a voltage of 0.25 V, with a power consumption of only 2.1 nW, corresponding to a FOM of 140.3 dB. The DC characteristics show an offset of 4.3 mV, a gain error of 2.5% (standard deviations), with an INL of 0.6%.

Resolution-independent fully differential SCI-based SAR ADC architecture using six unit capacitors

A resolution-independent successive approximation register (SAR) analog to digital converter (ADC) architecture based on a switched capacitor integrator is presented. Digital to analog converter (DAC) architecture uses charge sharing and integration principle for reference generation, using only six unit capacitors for a fully differential version. A 10-bit, 1.8-V and 0.9-MS/s SAR ADC is designed in 180-nm CMOS process. ADC architecture is area efficient when compared with SAR ADC with a binary weighted capacitor array DAC. The architecture is largely parasitic insensitive, also programmable resolution is possible with no hardware overhead.

Ultra-Low-Voltage Inverter-Based Amplifier with Novel Common-Mode Stabilization Loop

This work presents a single-stage, inverter-based, pseudo-differential amplifier that can work with ultra-low supply voltages. A novel common-mode stabilization loop allows proper differential operations, without impacting over the output differential performance. Electrical simulations show the effectiveness of this amplifier for supply voltages in the range of 0.3–0.5 V. In particular, a dc voltage gain of 25.16 dB, a gain-bandwidth product of 131.9 kHz with a capacitive load of 10 pF, and a static current consumption of only 557 nA are estimated at VDD = 0.5 V. Moreover, the circuit behavior with respect to process and temperature variations was verified. Finally, the proposed amplifier is employed in a switched-capacitor integrator and in a sample-and-hold circuit to prove its functionality in case-study applications.

Open-Loop Switched-Capacitor Integrator for Low Voltage Applications

An architecture of a switched-capacitor integrator that includes a charge buffer operating in an open-loop is hereby proposed. As for the switched-capacitor filters, the gain of the proposed integrator, which is given by the input/output capacitor ratio, ensures desensitization to process, voltage, and temperature variations. The proposed circuit is suitable for low voltage supplies. It enables a significant power saving compared to a traditional switched-capacitor integrator. This was demonstrated through an analytical comparison between the proposed integrator and a traditional switched-capacitor integrator. The mathematical results were supported and verified by simulations performed on a circuit prototype designed in 16 nm finFET technology with 0.95 V supply. The proposed switched-capacitor integrator consumes 76 µW, resulting in more than twice the efficiency for the traditional closed-loop switched-capacitor filter as an input voltage equal to 31.25 mV at 7 ns clock period is considered. The comparison of architectures was led among the proposed integrator and the state-of-the-art technology in terms of the figure of merit.

A Discrete-Time Audio $\Delta\Sigma$ Modulator Using Dynamic Amplifier With Speed Enhancement and Flicker Noise Reduction Techniques

This article presents a discrete-time second-order $\Delta \Sigma $ modulator for the audio applications. In this modulator, a novel dynamic amplifier is proposed to realize the switched-capacitor (SC) integrators. To eliminate the common-mode (CM) voltage drop in a closed-loop dynamic amplifier during the integration phase, without the use of additional load capacitance, the reset method for the amplifier is modified. Two auxiliary branches are introduced to enhance the settling speed of the integrator. Two different flicker noise reduction techniques (FNRTs) are developed to improve the signal-to-noise-and-distortion ratio (SNDR) (about 2 dB in the audio bandwidth). The prototype modulator is fabricated in 65-nm CMOS technology with a 0.12-mm2 core area, which achieves a dynamic range (DR) of 91 dB and a peak SNDR of 89.6 dB in the 24-kHz signal bandwidth. It consumes only 49- $\mu \text{W}$ power from a 0.8-V supply, translating into a Schreier figure of merit (FoM) of 176.5 dB.

Single low‐gain amplifier compensated hybrid delta‐sigma modulator

This article presents low-power circuit design techniques to achieve third-order noise shaping by employing multiple stages of passive switched-capacitor gain-boosted integrator and a passive switched-capacitor integrator. First integrator is a passive switched-capacitor for higher linearity. Second integrator is a three-stage passive switched-capacitor gain-boosted integrator to provide passive gain to the loop filter as well as the second DAC feedback. While the third integrator is a two-stage passive switched-capacitor gain-boosted integrator to provide passive gain as well as third DAC feedback for higher stability. Multiple lower stages of passive switched-capacitor gain-boosted integrators employed to enhance the noise shaping order of the modulator and suppress the parasitic effect. The preamplifier is the only active block, while the dynamic comparator used as single-bit quantiser. The complete transistor level with thermal noise simulation can achieve 84 dB of dynamic range (DR), 78.2 dB signal-to-noise-plus-distortion ratio (SNDR), and 78.5 dB signal-to-noise ratio (SNR) for 500 Hz signal bandwidth. It can also achieve signal-to-spurious-free dynamic range (SFDR) of 78.2 dB with estimated power consumption of 220 nW at 1 V supply voltage in SMIC 28 nm CMOS Technology. Finally, it can achieve state-of-the-art Walden Figure-of- Merit (FoM W ) of 33 fJ/Conv-Step and Schreier FoM S of 171.2 dB.