Switched-capacitor Implementation Research Articles

Fully differential implementation of a delta-sigma modulator based on the pseudo-pseudo differential technique

Flicker noise and distortion are the main limitations in biomedical applications, especially for Switched Capacitor implementations, where the flicker noise is folded into the signal band. To remove the flicker noise and increase the linearity, the Pseudo-Pseudo Differential (P2D) technique has been proposed, where a single-ended signal is processed in a differential way. This paper presents the first silicon implementation of a second order Comparator-Based Switched-Capacitor (CBSC) delta-sigma modulator based on a variation of the P2D technique. Experimental results in a standard 180 nm CMOS technology show an improvement of 10 dB in the Peak SNDR, 5 dB in the DR, and 9 dB in the SFDR over its pseudo differential counterpart, which is the preferred differential implementation for CBSC circuits. Moreover, it is achieved with a reduction in the power consumption.

Analysis of feedback predictive encoder based ADCs

PurposeThe purpose of this paper is to present analysis of the feedback predictive encoder-based analog-to-digital converter (ADC).Design/methodology/approachThe use of feedback predictive encoder-based ADCs presents an alternative to the traditional two-stage pipeline ADC by replacing the input estimate producing first stage of the pipeline with a predictive loop that also produces an estimate of the input signal.FindingsThe overload condition for feedback predictive encoder ADCs is dependent on input signal amplitude and frequency, system gain and filter order. The limitation on the practical usable filter order is set by limit cycle oscillation. A boundary condition is defined for determination of maximum usable filter order. In a practical implementation of the predictive encoder ADC, the time allocated to the key functions of the gain stage and loop quantizer leads to optimization of the power consumption.Practical implicationsA practical switched capacitor implementation of the predictive encoder-based ADC is proposed. The power consumption of key circuit blocks is investigated.Originality/valueThis paper presents a methodology to optimize the bandwidth of predictive encoder ADCs. The overload and stability conditions may be used to determine the maximum input signal bandwidth for a given loop quantizer. Optimization of power consumption based on the allocation of time between the gain stage and the successive approximation register ADC operation is investigated. The lower bound of power consumption for this architecture is estimated.

Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters

A novel technique for the digital background calibration of time-interleaved analog-to-digital converters is proposed. The technique corrects at the same time for both errors due to gain, offset and timing mismatches among the time-interleaved channels and errors due to nonlinearities in the channels, for instance due to capacitor mismatches in switched capacitor implementations. This feature, together with the use of the recursive least mean squares algorithm, makes the technique particularly fast (12 bits of accuracy can be achieved after about 4000 samples for a two-channel converter). The proposed calibration technique employs wideband differentiators, thus enabling digital background calibration of timing skews even with wideband input signals. Besides, undersampled differentiator filters are proposed, and it is shown that the technique is capable of calibrating undersampling converters by estimating the derivative of wideband input signals even outside the first Nyquist band.

Optimizing Capacitance Ratio Assignment for Low-Sensitivity SC Filter Implementation

Accurate capacitance matching is essential for switched-capacitor filters implementation because the filter coefficients depend upon the capacitance ratios. The use of identical unit capacitors in parallel to form larger capacitances and careful layout design can provide, in many cases, an accuracy of 0.1%. Unfortunately, this technique can be directly applied only if the filter coefficients are rational numbers. In general, coefficient approximations are required, leading to frequency response errors. In this paper, a new design method, using a genetic algorithm, is proposed to find the optimum capacitance ratio approximations by rational numbers which minimize the total number of unit capacitors for a given acceptable frequency response error, in order to save die area.

Performance Analysis of a Hybrid Incremental and Cyclic A/D Conversion Principle

This paper presents a new hybrid A/D conversion principle based on the combination of an incremental conversion for the most significant part of the result and on a cyclic conversion for the least significant part. The proposed approach exhibits a resolution comparable to a multiorder sigma-delta A/D converter (ADC), but with a higher conversion rate (typically a factor of two) and/or a lower complexity, at the cost of a more stringent antialiasing filter requirement. After having presented the basic equations of the conversion principle, a theoretical analysis of the resolution limitations is given, based on nonidealities and noise considerations. Finally, a switched-capacitor implementation example is given with the corresponding simulations, consisting of a low-complexity 14-b ADC suited for applications requiring medium-speed and very compact ADC.

A Third-Order 9-Bit 10-MHz CMOS $\Delta \Sigma $ Modulator With One Active Stage

We present a wideband architecture for DeltaSigma modulators using a single active stage and two switched capacitor passive stages. The mixed active-passive implementation has performance advantages over traditional switched-capacitor (SC) or continuous-time implementations, particularly for high-resolution, wideband applications with high sampling rates and moderate oversampling ratios. Design insensitivity to clock jitter and process variations is achieved by the good choice of the modulator architecture. The proposed modulator is designed in 0.13-mum CMOS technology and meets all major requirements for application in IEEE 802.16 wireless MAN receivers. Circuit simulations show that the modulator with a single bit quantizer consumes 5.5 mW from a 1.2-V power supply and achieves a 9-bit resolution over a 10-MHz bandwidth at an OSR of 32. Good performance is also achieved for lower bandwidth applications.

Linearity analysis in pipeline A/D converters

AbstractA method for estimating integral nonlinearity (INL) in pipeline analog‐to‐digital converters is presented. In this method, errors in each stage are modeled by an equivalent input‐referred gain error and an input‐referred nonlinearity. For a switched capacitor implementation, the proposed model predicts the maximum statistical INL in terms of capacitor mismatch and also provides an exact formula for INL in terms of finite gain of operational amplifiers. Using this model, it is proved that a high per‐stage resolution reduces the power consumption in low‐speed converters, whereas in high‐speed circuits 1.5‐bit or 2.5‐bit stage is more advantageous. It is also shown that when voltage swing is below 1 V, the lower limit for the size of the capacitors is mainly determined by thermal noise rather than by INL. Copyright © 2008 John Wiley & Sons, Ltd.

Resonation-based cascade modulator for broadband low-voltage A/D conversion

A novel cascade ΣΔ modulator architecture is presented that employs inter-stage resonation to increase its effective resolution compared to traditional cascades while presenting very relaxed output swing requirements and, subsequently, high robustness to nonlinearities of the amplifiers. In addition, the use of loop filters based on forward-Euler integrators, instead of backward-Euler integrators as proposed in earlier approaches, simplifies the switched-capacitor implementation and makes the proposed architecture very suited to wideband A/D conversion.

A 10-bit 44-MS/s 20-mW Configurable Time-Interleaved Pipeline ADC for a Dual-Mode 802.11b/Bluetooth Receiver

This work presents a configurable time-interleaved pipeline architecture as an efficient solution for the ADC design in high data rate multi-standard radios. The ADC is implemented in a 0.25-/spl mu/m BiCMOS process as part of an integrated dual mode 802.11b/Bluetooth direct conversion receiver. Its structure can be configured to accommodate the different sampling rate and dynamic range requirements of both standards. The different techniques employed at the system and circuit levels to optimize the power consumption are described. An on-line digital calibration scheme is also incorporated to assure the conversion linearity and reduce mismatch among the parallel branches. The proposed ADC is a switched-capacitor implementation occupying an area of 2.1 mm/sup 2/. It achieves 60 dB/64 dB dynamic range at 44 MHz/11 MHz sampling frequency with a power consumption of 20.2 mW/14.8 mW for the 802.11b/Bluetooth baseband signals.

Quadrature /spl Sigma//spl Delta/ modulators with a dynamic element matching scheme

This paper presents a new topology of a multibit quadrature bandpass sigma-delta modulator which employs a simple dynamic element matching (DEM) technique in order to reduce the effects of path mismatch, namely aliasing in the signal band of the mirror images of the signal and of the quantization noise. The DEM scheme results in a reduction of the aliasing of the quantization noise mirror image while it reduces the input signal mirror image alias problem to a self-image problem. It is shown that the self-image can be completely removed in switched-capacitor implementations by using the same capacitors to sample the input and the reference of the feedback digital-analog converters (DACs). Moreover, a simple method for extending low-pass mismatch noise shaping techniques to the complex bandpass case is proposed for the case of multibit feedback DACs.

Low power delta-sigma Modulator for ADSL applications in a low-Voltage CMOS technology

This paper examines the design and implementation of a fourth-order low-pass delta-sigma modulator using a systematic top-down design methodology. Special effort has been made to reduce the power consumption of the modulator through careful system-level modeling and synthesis of circuit specifications. Tradeoffs between circuit building block specifications, optimization time and computing resources are derived. This system-level modeling was tested through the successful implementation of a switched-capacitor delta-sigma analog-to-digital converter integrated circuit (IC) with an output rate slightly exceeding 2 MS/s, in a 1.8-V 0.18-/spl mu/m, single-polysilicon six-metal standard CMOS process. When sampled at 50 MHz, experimental results reveal that the IC achieves 77.6-dB dynamic range. The prototype consumes 18.8 mW of power, making it one of the lowest power dissipations in switched-capacitor implementations, and for applications where output rates exceed 2 MS/s. When compared to other state-of-the-art switched-capacitor modulators using a widely adopted figure of merit, the modulator dissipates less power and offers superior overall performance.

Domino Free 4-Path Time-Interleaved Second Order Sigma-Delta Modulator

A domino free 4-path time-interleaved second order sigma-delta modulator is proposed. This time-interleaved scheme uses only one integrator channel along with incomplete integrator output terms to completely eliminate the quantizer domino which is a key limit for the practical circuit implementation of conventional multi-path time-interleaved sigma-delta modulators. In addition, the single integrator channel leads to considerable hardware reduction as well as path mismatch insensitivity, since only one global feedback path is required. As a result, the switched capacitor implementation of the 4-path time-interleaved second order sigma-delta modulator is enabled with the conventional 2-phase clocking scheme by using only 5 op-amps.

A Double-Sampling Extended-Counting ADC

Extended-counting analog-to-digital conversion combines the accuracy of /spl Sigma//spl Delta/ modulation with the speed of algorithmic conversion. In this paper, a double-sampling technique is introduced for this type of converter. It is based on a variant of the fully floating bilinear integrator. This way, the clock frequency of the converter is almost halved. An experimental converter was designed in a 0.6-/spl mu/m CMOS technology for a bandwidth of 500 kHz at a 3.3-V supply. In the switched-capacitor implementation, the hardware is extensively reused. This way, the converter can be realized with only one operational amplifier. On the other hand, compared to alternative implementations, the amount of switches is increased. These are designed carefully in order not to degrade the performance. The converter converts a sample in 24 clock cycles and achieves a dynamic range of 87 dB. The peak signal-to-noise ratio (SNR) and signal-to-noise-plus-distortion ratio (SNDR) were measured to be 82 and 81 dB, respectively. The power consumption was 28-mW analog and 20-mW digital. The converter core occupies 0.7 mm/sup 2/ including digital logic.

A 250-khz 94-db double-sampling ΣΔ modulation a/d converter with a modified noise transfer function

This paper presents a high-order double-sampling single-loop /spl Sigma//spl Delta/ modulation analog-to-digital (A/D) converter. The important problem of noise folding in double-sampling circuits is solved here at the architectural level by placing one of the zeros in the modulator's noise transfer function at half the sampling frequency instead of in the baseband. The resulting modulator is of fifth order but has the baseband performance of a fourth-order modulator. Through the use of an efficient switched-capacitor implementation, the overall circuit uses only four operational amplifiers and hence, its complexity is similar to that of a fourth-order modulator. An experimental 1-bit modulator was designed for an oversampling ratio of 96 and a bandwidth of 250 kHz at a 3.3-V supply in a conservative 0.8-/spl mu/m standard CMOS process. Due to the double-sampling, the sampling frequency is 48 MHz, although the circuits operate at a clock frequency of only 24 MHz. The circuit achieves a dynamic range of 94 dB. The peak signal-to-noise ratio and signal-to-noise-plus-distortion ratio were measured to be 90 and 86 dB, respectively. The power consumption of the complete circuit including clock drivers and output pad drivers was 43 mW. The analog blocks (opamps, comparators, etc.) consume 30 mW of this total.

Sigma-delta modulator with spectrally shaped feedback

This paper explores the use of finite-impulse response (FIR) filters in the feedback path of a low-pass sigma-delta modulator in order to combat some nonideal effects encountered in an analog implementation. In this approach, the filter corresponding to the first integrator is a lowpass filter which smoothes out the feedback waveform by attenuating the high-frequency quantization noise. This lowpass filtering decreases the power consumption of a switched-capacitor implementation and alternatively reduces the sensitivity to clock jitter in a continuous-time structure. A design methodology ensuring the stability of the system is presented. Theoretical analysis and simulations show that the FIR filters allow a continuous-time single-bit modulator to achieve the jitter performance of a comparable multibit modulator.

Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping

A 1-V 1-mW 14-bit /spl Delta//spl Sigma/ modulator in a standard CMOS 0.35-/spl mu/m technology is presented. Special attention has been given to device reliability and power consumption in a switched-capacitor implementation. A locally bootstrapped symmetrical switch that avoids gate dielectric overstress is used in order to allow rail-to-rail signal switching. The switch constant overdrive also enhances considerably circuit linearity. Modulator coefficients of a single-loop third-order topology have been optimized for low power. Further reduction in the power consumption is obtained through a modified two-stage opamp. Measurement results show that for an oversampling ratio of 100, the modulator achieves a dynamic range of 88 dB, a peak signal-to-noise ratio of 87 dB and a peak signal-to-noise-plus-distortion ratio of 85 dB in a signal bandwidth of 25 kHz.

A mismatch-independent DNL pipelined analog-to-digital converter

A novel approach for CMOS pipelined analog-to-digital conversion based on switched-capacitor implementation is proposed. This converter's differential nonlinearity (DNL) is independent of any element mismatches in residue amplification. Derivations of the causes on DNL errors in conventional architectures are presented. The DNL of any pipelined converter is dependent upon the conditioning of the residue in the sub-digital-to-analog converter (sub-DAC) and interstage gain stages more than in the choice threshold of the sub-analog-to-digital converter. With well-conditioned residue, any errors made in the sub-DAC's of any earlier stage are evenly distributed over the range of subsequent stages' digital codes. This property is exploited in the design of the proposed converter, which achieves a measured 12 bit resolution and a simulated resolution of 13 bits, even under a 5% mismatch in capacitor ratios. The prototype is implemented using an operational transconductance amplifier with gain boosting. The ADC runs at 10 MHz (3.3 Ms/s).

An eighth-order bandpass ΔΣ modulator for A/D conversion in digital radio

This paper examines the design and implementation of an eighth-order bandpass delta-sigma modulator. The design process is investigated from the signal flow graph level, through to the details of the switched capacitor implementation and layout considerations. Simulation results, highlighting the effects of process variation, are provided and the experimental performance of the modulator described. The modulator is implemented in a 0.8-/spl mu/m BiCMOS process and occupies an active area of 1.7 mm/sup 2/. Operating from /spl plusmn/2.5-V supplies, the fabricated prototype exhibits stable behaviour and achieves a dynamic range of 67 dB over a 200-kHz bandwidth centered at the commonly used intermediate frequency of 10.7 MHz. This paper, therefore, demonstrates the viability of high-order single-bit bandpass delta-sigma modulation.

Polyphase SC IIR Hilbert transformers

A novel polyphase switched-capacitor (SC) implementation of IIR Hubert transformers is proposed. The circuit employs fewer op-amps and has better performance than the traditional two-phase circuit. SWIT-CAP2 simulation results and phase sensitivities to capacitance mismatches are provided.

A 1.95-V, 0.34-mW, 12-b sigma-delta modulator stabilized by local feedback loops

The design of a low-power, low-voltage, 12-b 8-kHz bandwidth /spl Sigma//spl Delta/ modulator for high-quality voice that consumes only 0.34 mW at 1.95 V supply is described. The modulator employs a special architecture in which a third-order modulator is stabilized by a local feedback loop around each integrator. Unlike multistage /spl Sigma//spl Delta/ modulators, this architecture is very tolerant to the modest dc gain of low voltage op-amps. The architecture, together with special circuit techniques, permits a low-voltage switched capacitor implementation at 1.95 V-3.3 V supply using standard 1.2-/spl mu/m CMOS technology.